Post on 05-Apr-2018
8/2/2019 Stage Cpld Correction
1/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
3
Travaux pratiques
Les travaux proposs sont extraits du sujet du baccalaurat gnie lectronique de
lAcadmie de Toulouse. Pour ce stage, ltude sera la commande du lve vitre de la R25.
Cahier des charges simplifi :
Entres :
N_MO : Normal monte : Une action maintenue sur ce bouton poussoir actionne le
moteur dans le sens de la monte.
N_DE : Normal descente : Une action maintenue sur ce bouton poussoir actionne le
moteur dans le sens de la descente.
S_MO : Squentiel monte : Une impulsion sur ce bouton poussoir actionne le moteur
dans le sens de la monte.
S_DE : Squentiel descente : Une impulsion sur ce bouton poussoir actionne le moteur
dans le sens de la descente.
I_MOT : Intensit moteur : Cette entre simule lintensit du courant dans le moteur.
Lorsque lintensit du courant dpasse une valeur dtermine, un niveau logique haut
apparat sur cette entre.
Reset : Une impulsion sur ce bouton poussoir remet la machine tat dans ltat initial.
H : Horloge qui assure le changement dtat.
Lorsque la vitre est en mouvement, une action sur une entre produit larrt du moteur.
Sorties :
DE : Niveau haut qui provoque la rotation du moteur qui provoque la descente de la vitre
MO : Niveau haut qui provoque la rotation du moteur qui provoque la monte de la vitre
8/2/2019 Stage Cpld Correction
2/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
4
Correction du travail demand : TP1
Q 10) Donner le digramme de fonctionnement laide des machines tats
//d iag ram ACTIONS//d iag ram ACTIONS
R25S_DE
UP
S_MO
N_MO
Reset
H
MAE
N_DE DW
I_MOT
S1
Reset='1'
UP
8/2/2019 Stage Cpld Correction
3/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
5
architecture r25_arch of r25 is
-- SYMBOLIC ENCODED state machine: MAEtype MAE_type is (S1, S2, S3, S6, S7);signal MAE: MAE_type;
begin--concurrent signal assignments
--diagram ACTIONS;
MAE_machine: process (H)
begin
if H'event and H = '1' thenif Reset='1' then
MAE
8/2/2019 Stage Cpld Correction
4/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
6
Q 12) Compiler pour placer la structure dans un PAL 16V8
| | | | | | |
_________________
-| |-
-| |--| |-
-| CYPRESS |-
-| |-
-| |- Warp VHDL Synthesis Compiler: Version 6.2 IR 1
-| |- Copyright (C) 1991-2001 Cypress Semiconductor|_______________|
| | | | | | |
======================================================================Compiling: R25.vhd
Options: -yu -e10 -w100 -o2 -ygs -fP -fUH -v10 -yw -dc16v8 -ppalce16v8l-15pc -b R25.vhd -u R25.hie
======================================================================
vhdlfe V6.2 IR 1: VHDL parser
Tue Mar 18 09:03:26 2003
Library 'work' => directory 'lc16v8'Linking 'C:\PROGRA~1\Cypress\Warp\bin\std.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\work\cypress.vif'.
Using control file 'R25.ctl'.Library 'ieee' => directory 'C:\PROGRA~1\Cypress\Warp\lib\ieee\work'
Linking 'C:\PROGRA~1\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Note: Using config. rule 'h' to set attribute 'pin_numbers' on 'h'.
Note: Using config. rule 'i_mot' to set attribute 'pin_numbers' on 'i_mot'.Note: Using config. rule 'n_de' to set attribute 'pin_numbers' on 'n_de'.
Note: Using config. rule 'n_mo' to set attribute 'pin_numbers' on 'n_mo'.
Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note: Using config. rule 's_de' to set attribute 'pin_numbers' on 's_de'.
Note: Using config. rule 's_mo' to set attribute 'pin_numbers' on 's_mo'.Note: Using config. rule 'dw' to set attribute 'pin_numbers' on 'dw'.
Note: Using config. rule 'up' to set attribute 'pin_numbers' on 'up'.
vhdlfe: No errors.
tovif V6.2 IR 1: High-level synthesis
Tue Mar 18 09:03:26 2003
Linking 'C:\PROGRA~1\Cypress\Warp\bin\std.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\work\cypress.vif'.Linking 'D:\Mon_travail\iufm\VHDL\R25\R25.ctl'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
tovif: No errors.
topld V6.2 IR 1: Synthesis and optimization
Tue Mar 18 09:03:26 2003
Linking 'C:\PROGRA~1\Cypress\Warp\bin\std.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\cypress.vhd'.
Linking 'C:\PROGRA~1\Cypress\Warp\lib\common\work\cypress.vif'.Linking 'D:\Mon_travail\iufm\VHDL\R25\R25.ctl'.Linking 'C:\PROGRA~1\Cypress\Warp\lib\ieee\work\stdlogic.vif'.
Note: Using config. rule 'h' to set attribute 'pin_numbers' on 'h'.
Note: Using config. rule 'i_mot' to set attribute 'pin_numbers' on 'i_mot'.
Note: Using config. rule 'n_de' to set attribute 'pin_numbers' on 'n_de'.Note: Using config. rule 'n_mo' to set attribute 'pin_numbers' on 'n_mo'.
Note: Using config. rule 'reset' to set attribute 'pin_numbers' on 'reset'.
Note: Using config. rule 's_de' to set attribute 'pin_numbers' on 's_de'.
Note: Using config. rule 's_mo' to set attribute 'pin_numbers' on 's_mo'.Note: Using config. rule 'dw' to set attribute 'pin_numbers' on 'dw'.
Note: Using config. rule 'up' to set attribute 'pin_numbers' on 'up'.
State variable 'mae' is represented by a Bit_vector (0 to 2).
State encoding (sequential) for 'mae' is:s1 := b"000";
s2 := b"001";
s3 := b"010";
8/2/2019 Stage Cpld Correction
5/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
7
s6 := b"011";
s7 := b"100";
----------------------------------------------------------Detecting unused logic.
----------------------------------------------------------
------------------------------------------------------Alias Detection
------------------------------------------------------
------------------------------------------------------
Aliased 0 equations, 0 wires.------------------------------------------------------
----------------------------------------------------------
Circuit simplification----------------------------------------------------------
----------------------------------------------------------
Circuit simplification results:
Expanded 0 signals.
Turned 0 signals into soft nodes.
Maximum expansion cost was set at 10.----------------------------------------------------------
Created 17 PLD nodes.
topld: No errors.
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
DESIGN HEADER INFORMATION (09:03:28)
Input File(s): R25.pla
Device : c16v8
Package : palce16v8l-15pcReportFile : R25.rpt
Program Controls:
COMMAND LANGUAGE_VHDLCOMMAND DefaultOE_open_H
COMMAND DefaultOE_open
COMMAND PROPERTY BUS_HOLD ENABLE
Signal Requests:
GROUP USEPOL ALL
GROUP SLOW_SLEW ALL
Completed Successfully
----------------------------------------------------------------------------
PLD Optimizer Software: DSGNOPT.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
OPTIMIZATION OPTIONS (09:03:28)
Messages:
Information: Process virtual 'maeSBV_2D' ... expanded.
Information: Process virtual 'maeSBV_1D' ... expanded.Information: Process virtual 'maeSBV_0D' ... expanded.
Information: Process virtual 'upD' ... expanded.
Information: Process virtual 'dwD' ... expanded.Information: Process virtual 'maeSBV_2' ... converted to NODE.Information: Process virtual 'maeSBV_1' ... converted to NODE.
Information: Process virtual 'maeSBV_0' ... converted to NODE.
Information: Optimizing logic using best output polarity for signals:
dw.D maeSBV_0.D maeSBV_1.D maeSBV_2.D up.D
Information: Selected logic optimization OFF for signals:
dw.C maeSBV_0.C maeSBV_1.C maeSBV_2.C up.C
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
8/2/2019 Stage Cpld Correction
6/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
8
----------------------------------------------------------------------------
PLD Optimizer Software: MINOPT.EXE 01/NOV/1999 [v4.02 ] 6.2 IR 1
LOGIC MINIMIZATION ()
Messages:
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------PLD Optimizer Software: DSGNOPT.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
OPTIMIZATION OPTIONS (09:03:28)
Messages:
Summary:Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
DESIGN EQUATIONS (09:03:28)
dw.D =
dw.Q * maeSBV_2.Q * /reset
+ maeSBV_1.Q * /maeSBV_2.Q * /reset
+ maeSBV_0.Q * /reset
dw.C =
h
maeSBV_0.D =
/i_mot * /maeSBV_1.Q * /maeSBV_2.Q * /n_de * /n_mo * /reset *
s_de * /s_mo
+ /i_mot * maeSBV_0.Q * /n_de * /n_mo * /reset * /s_mo
maeSBV_0.C =
h
maeSBV_1.D =
/i_mot * /maeSBV_0.Q * /maeSBV_1.Q * /maeSBV_2.Q * /n_de * /n_mo *
/reset * /s_de * s_mo
+ /i_mot * /maeSBV_0.Q * /maeSBV_2.Q * n_de * /n_mo * /reset */s_de * /s_mo
+ /i_mot * maeSBV_1.Q * maeSBV_2.Q * /n_de * /n_mo * /reset *
/s_de
maeSBV_1.C =
h
maeSBV_2.D =
/i_mot * /maeSBV_0.Q * /maeSBV_1.Q * /maeSBV_2.Q * /n_de * /n_mo */reset * /s_de * s_mo
+ /i_mot * /maeSBV_0.Q * /maeSBV_1.Q * /n_de * n_mo * /reset *
/s_de * /s_mo+ /i_mot * maeSBV_1.Q * maeSBV_2.Q * /n_de * /n_mo * /reset */s_de
maeSBV_2.C =
h
up.D =
maeSBV_1.Q * /reset * up.Q
+ maeSBV_0.Q * /reset * up.Q+ maeSBV_2.Q * /reset
up.C =
h
8/2/2019 Stage Cpld Correction
7/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
9
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
DESIGN RULE CHECK (09:03:28)
Messages:
None.
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
PINOUT INFORMATION (09:03:28)
Messages:
Information: Checking for duplicate NODE logic.None.
C16V8C__________________________________________
h =| 1| |20|* not used
s_mo =| 2| |19|* not used
s_de =| 3| |18|* not usedreset =| 4| |17|* not used
n_mo =| 5| |16|= (maeSBV_0)
n_de =| 6| |15|= dw
i_mot =| 7| |14|= (maeSBV_1)
not used *| 8| |13|= (maeSBV_2)not used *| 9| |12|= up
not used *|10| |11|* Reserved
__________________________________________
Summary:
Error Count = 0 Warning Count = 0
Completed Successfully
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
RESOURCE UTILIZATION (09:03:28)
Information: Macrocell Utilization.
Description Used Max
______________________________________
| Dedicated Inputs | 6 | 8 |
| Clock/Inputs | 1 | 1 || Enable/Inputs | 0 | 1 |
| Output Macrocells | 5 | 8 |
______________________________________
12 / 18 = 66 %
Information: Output Logic Product Term Utilization.
Node# Output Signal Name Used Max________________________________________
| 12 | up | 3 | 8 |
| 13 | maeSBV_2 | 3 | 8 |
| 14 | maeSBV_1 | 3 | 8 || 15 | dw | 3 | 8 |
| 16 | maeSBV_0 | 2 | 8 |
| 17 | Unused | 0 | 8 |
| 18 | Unused | 0 | 8 || 19 | Unused | 0 | 8 |
________________________________________
14 / 64 = 21 %
Completed Successfully
8/2/2019 Stage Cpld Correction
8/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
10
----------------------------------------------------------------------------
PLD Compiler Software: PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
JEDEC ASSEMBLE (09:03:28)
Messages:
Information: Output file 'R25.jed' created.
Summary:
Error Count = 0 Warning Count = 0
Q 13) Simuler, donner le chronogramme, valider le fonctionnement
Travail demand : TP2
8/2/2019 Stage Cpld Correction
9/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
11
Q 14) Saisir la structure dans protus
A5
A0
A2
A7
A1A3A6
A4A5A7
A0A1A2A3A4
A7
A9
A0
A9
A6
A6
A1
A2
A3
A4
A5
CLK/I01
I12
I23
I34
I45
I56
I67
I78
I89
OE/I911
IO019
IO118
IO217
IO316
IO415
IO514
IO613
IO712
U1
AM16V8
2345678
1
RP1
10k
VCC
H1
H1
5V
VCC
C1
10nF
Q1BC337
RL15V
5V
R1220
Q2BC337
RL25V
5V
R2220
+12
+88.8
MOTMOT
R30.2
+12
SW1
S_MO SW2
N_MO
SW3
S_DE
SW4
N_DE
SW5
I_MOT
Amps
+88.
8
Q 15) Placer le code JEDECypress C16V8C Jedec Fuse File: R25.jed
This file was created on 03/18/2003 at 09:03:28
by PLA2JED.EXE 31/03/2000 [v4.02 ] 6.2 IR 1
C16V8CQP20* Number of Pins*
QF2194* Number of Fuses*
F0* Note: Default fuse setting 0*
G0* Note: Security bit Unprogrammed*NOTE DEVICE C16V8C*
NOTE PACKAGE palce16v8l-15pc*
NOTE PROPERTY BUS_HOLD ENABLE*
NOTE PINS h:1 s_mo:2 s_de:3 reset:4 n_mo:5 n_de:6 i_mot:7 up:12 dw:15 *NOTE PINS *
NOTE PINS maeSBV_2:_13 maeSBV_1:_14 maeSBV_0:_16 *
L00000
1111111111111111111111111111111100000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
* Node [19] => OE : 1 ,LOGIC : 7 *
L00256
8/2/2019 Stage Cpld Correction
10/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
12
11111111111111111111111111111111
00000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000* Node [18] => OE : 1 ,LOGIC : 7 *
L00512
11111111111111111111111111111111
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
* Node [17] => OE : 1 ,LOGIC : 7 *
L00768
10110111101110111011101011101111
10111111101110011011101111111111
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
* Node maeSBV_0[16] => LOGIC : 8 *
L01024
1111111110111111110111111101111111111111101111111111110111101111
11111111101111011111111111111111
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
* Node dw[15] => LOGIC : 8 *
L01280
011110111011101010111010111011111011101110111010011110111110111111111011101110111011100111011111
00000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
* Node maeSBV_1[14] => LOGIC : 8 *
L01536
01111011101110101011101011101111
10111011101101101011101011111111
11111011101110111011100111011111
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000* Node maeSBV_2[13] => LOGIC : 8 *
L01792
1111111110111111111111011111110111111111101111011111111111111101
11111111101111111111111111011111
00000000000000000000000000000000
0000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000
00000000000000000000000000000000
* Node up[12] => LOGIC : 8 *
L02048
8/2/2019 Stage Cpld Correction
11/11
IUFM Midi Pyrnes CV Stage CPLD mars 2003-03-18
13
11111111* Note: POLARITY FUSES CL1x*
L02056
00000000000000000000000000000000
0000000000000000
0000000000000000* Note: SIGNATURE FUSES*
L02120
11100000* Note: 12 *
L02128
1100000011000000110000001100000011100000111000001110000011100000* Note: PT CONNECT FUSES FOR POWER SAVINGS*
L02192
01* Note: CG0 CG1*
C3B7B* Note: Fuse Checksum*
L00000111111111111111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*
L002561111111111111111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L005121111111111111111111111111111111100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*
L0076810110111101110111011101011101111101111111011100110111011111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000
00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L010241111111110111111110111111101111111111111101111111111110111101111111111111011110111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L01280
0111101110111010101110101110111110111011101110100111101111101111111110111011101110111001110111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L01536
0111101110111010101110101110111110111011101101101011101011111111111110111011101110111001110111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L017921111111110111111111111011111110111111111101111011111111111111101111111111011111111111111110111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000*L02048 11111111*
L02056 0000000000000000000000000000000000000000000000000000000000000000*L02120 11100000*L02128 1100000011000000110000001100000011100000111000001110000011100000*
L02192 01*