Digital Integrated Circuits A Design...
Transcript of Digital Integrated Circuits A Design...
Digital IC Introduction
Digital Integrated Circuits
A Design Perspective Designing Combinational Logic Circuits
Fuyuzhuo School of Microelectronics,SJTU
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Static CMOS logic • CMOS static characteristic • CMOS propagate delay • Large fan-in technology • Logic effort • CMOS power analysis
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Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is
constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum
speed? • We have already solved this for the inverter chain – can
we generalize it for any type of logic?
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)f(0 γgptt pp +=
4
Modified formula
)f1()1( 00 γγ+=+= p
g
extpp t
CCtt
Electric effort
logic effort Intrinsic ratio Rpar=Rinv
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Modified formula �
5
)(
)(
)(
)(.2ln
).(2ln
0
0
0
γ
γ
gfpt
CC
CC
CC
t
CC
CC
CC
t
CC
CC
CC
CR
RCCttt
p
g
ext
ginv
g
int
parp
g
ext
int
g
int
parp
g
ext
int
g
int
parintinv
parextparextparp
+=
+=
+=
+=
+=+=
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Outline about logic effort • Introduction • Delay in a Logic Gate • Multistage Logic Networks • Choosing the Best Number of Stages • Example • Summary
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Introduction • Chip designers face a bewildering array of choices
• What is the best circuit topology for a function? • How many stages of logic give least delay? • How wide should the transistors be?
• Logical effort is a method to make these decisions • Uses a simple model of delay • Allows back-of-the-envelope calculations • Helps make rapid comparisons between alternatives • Emphasizes remarkable symmetries
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Delay in a Logic Gate • Express delays in process-independent unit
• Delay has two components
• Effort delay h= gf (a.k.a. stage effort) • Again has two components
• f: electrical effort = Cout / Cin
• Ratio of output to input capacitance • Sometimes called fanout
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absddτ
=
hpd +=
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Delay in a Logic Gate • Express delays in process-independent unit
• Delay has two components
• Parasitic delay p • Represents delay of gate driving no load • Set by internal parasitic capacitance
absddτ
=
hpd +=
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Delay Plots d = h + p
= gf + p
• What about NOR2?
Electrical Effort:f = Cout / Cin
Nor
mal
ized
Del
ay: d
Inverter2-inputNAND
g = 1p = 1d = f + 1
g = 4/3p = 2d = (4/3)f + 2
Effort Delay: h
Parasitic Delay: p
0 1 2 3 4 5
0
1
2
3
4
5
6
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Computing Logical Effort • DEF: Logical effort is the ratio of the input capacitance of
a gate to the input capacitance of an inverter delivering the same output current.
• Measure from delay vs. fanout plots • Or estimate by counting transistor widths
A Y A
B
YA
BY
1
2
1 1
2 2
2
2
4
4
Cin = 3g = 3/3
Cin = 4g = 4/3
Cin = 5g = 5/3
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Catalog of Gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
• Logical effort of common gates
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Catalog of Gates
Gate type Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
• Parasitic delay of common gates • In multiples of pinv (≈1)
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Example: FO4 Inverter • Estimate the delay of a fanout-of-4 (FO4) inverter • Logical Effort: g = 1
Electrical Effort: f = 4 Parasitic Delay: p = 1 Stage Delay: d = 5
d
The FO4 delay is about
200 ps in 0.6 µm process
60 ps in a 180 nm process
f/3 ps in an f µm process
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Multistage Logic Networks • Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
iG g=∏
10x
y z20
g1 = 1f1 = x/10
g2 = 5/3f2 = y/x
g3 = 4/3f3 = z/y
g4 = 1f4 = 20/z
pathin
pathout
CC
F−
−=
∏∏ ==N
ii
N
i gfhH11
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Multistage Logic Networks • Logical effort generalizes to multistage networks
Path Logical Effort
Path Electrical Effort
Path Effort
iG g=∏
pathin
pathout
CC
F−
−=
∏∏ ==N
ii
N
i gfhH11
Can we write H = GF? F counts once and f not.
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Paths that Branch • G = 1
F = 90 / 5 = 18 GF = 18 f1 = (15 +15) / 5 = 6 f2 = 90 / 15 = 6 H = g1g2f1f2 = 36 = 2GF
5
15
1590
90No! Consider paths that branch
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Multistage Logic Networks • Can we write H = GF?
• Fcount once and f not.
• H >=GF
iG g=∏N
L
pathin
pathout
CC
CC
CC
CC
F ...2
3
1
2==−
−
NN
ii
N
i hgfhH === ∏∏11
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Branching Effort • Introduce branching effort
• Accounts for branching between stages in path
• Now we compute the path effort • H = GBF
on path off path
on path
C Cb
C+
=
iB b=∏Note: GFBgfhHN
ii
N
i === ∏∏11
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It is just like inverter chain! �
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)()(
)(.2ln
100
i
iiipp
g
ext
ginv
g
ginv
parginvinvp
C
Cgpt
gfpt
C
C
C
C
C
CCRt
++=+=
+=
γγ The only size related par.
iiii
i
ii
i
ii
ii
i
i
fgfg
C
Cg
C
Cg
C
Cg
C
g
i
=
=
=
−−
+
+
11
1
1-
1-
2
1
1-
1- 0-1
γγ
γγ
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Designing Fast Circuits • Delay is smallest when each stage bears same effort
• Thus minimum delay of N stage path is
• This is a key result of logical effort • Find fastest possible delay • Doesn’t require calculating gate sizes
Nii Hfgh
1
==
)(1
0 γNhptD
N
jjp += ∑
=
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Gate Sizes • How wide should the gates be for least delay?
• Working backward/forward, apply capacitance transformation to find input capacitance of each gate given load it drives.
• Check work by verifying input cap spec is met.
hcg
C
ccggfh
i
i
outiin
in
out
=⇒
==
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Derivation • Consider adding inverters to end of path
• How many give least delay?
• Define best stage effort N - n1 Extra InvertersLogic Block:n1 Stages
Path Effort F
0ln
)(
111
11
1 1
=++−=∂
∂
−++= ∑=
invNNN
inv
n
ii
N
pHHHND
pnNpNHD
0)ln1(
1
=+−
=
inv
N
phhHh
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Best Stage Effort • has no closed-form
solution • Neglecting parasitics (pinv = 0), find h = 2.718 (e) • For pinv = 1, solve numerically for h= 3.59
0)ln1( =−+ hhpinv
)(loglog
)(
log
11
11
1
1
nHpHh
nNpNhD
HN
h
n
iih
n
ii
h
−++=
−++=
=
∑
∑
=
=
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Sensitivity Analysis • How sensitive is delay to using exactly the best number
of stages?
• 2.4 < h< 6 gives delay within 15% of optimal • We can be sloppy! • I like h= 4
1.0
1.2
1.4
1.6
1.0 2.00.5 1.40.7
N / N
1.151.26
1.51
(ρ =2.4)(ρ=6)
D(N)
/D(N)
0.0
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Gate Sizes & Delay Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: H = GBF = 154 Stage Effort: h =H1/3=5.36 Path Delay: D =4h+1+4+1+1=7+14.08=21.1 Gate sizes: z = 96*1/5.36 = 18 y = 18*2/5.36 = 6.7
A[3] A[3] A[2] A[2] A[1] A[1] A[0] A[0]
word[0]
word[15]
96 units of wordline capacitance
10 10 10 10 10 10 10 10
y z
y z
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Comparison • Compare many alternatives with a spreadsheet
Design N G P D
NAND4-INV 2 2 5 29.8
NAND2-NOR2 2 20/9 4 30.1
INV-NAND4-INV 3 2 6 22.1
NAND4-INV-INV-INV 4 2 7 21.1
NAND2-NOR2-INV-INV 4 20/9 6 20.5
NAND2-INV-NAND2-INV 4 16/9 6 19.7
INV-NAND2-INV-NAND2-INV 5 16/9 7 20.4
NAND2-INV-NAND2-INV-INV-INV 6 16/9 8 21.6
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Review of Definitions Term Stage Path
number of stages N
logical effort g
electrical effort f = Cout/Cin F= Cout-path/Cin-path
branching effort
effort h =gf H=GBF
effort delay h
parasitic delay p
delay d = p+f
iG g=∏
iB b=∏
iP p=∑
on-path off-path
on-path
C CCb +
=
∑= iF hD
PDD F +=
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Method of Logical Effort 1) Compute path effort H=GBF(G=1) 2) Estimate best number of stages N=log4H 3) Sketch path with N stages 4) Re-compute G 5) Determine best stage effort h=GBF1/N=H1/N 6) Estimate least delay D=P+h*N 7) Find gate sizes
hcg
C
ccggfh
i
i
outiin
in
out
=⇒
==
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Limits of Logical Effort • Chicken and egg problem
• Need path to compute G • But don’t know number of stages without G
• Simplistic delay model • Neglects input rise time effects
• Interconnect • Iteration required in designs with wire
• Maximum speed only • Not minimum area/power for constrained delay
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Summary • Numeric logical effort characterizes gates • NANDs are faster than NORs in CMOS • Paths are fastest when effort delays are ~4 • Path delay is weakly sensitive to stages, sizes • But using fewer stages doesn’t mean faster
paths • Delay of path is about log4H stage
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P/N ratio related to logic effort • Bubble Pushing • Compound Gates • Logical Effort Example • Input Ordering • Asymmetric Gates • Skewed Gates • Best P/N ratio
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Asymmetric Gates � • Asymmetric gates favor one input over another • Ex: suppose input A of a NAND gate is most critical
• Use smaller transistor on A (less capacitance) • Boost size of noncritical input • So total resistance is same
• gA = 10/9 • gB = 2 • gtotal = gA + gB = 28/9 • Asymmetric gate approaches g = 1 on critical input • But total logical effort goes up
Areset
Y
4
4/3
22
reset
AY
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Skewed Gates • Skewed gates favor one edge over another • Ex: suppose rising output of inverter is most critical
• Downsize noncritical nMOS transistor
• Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. • gu = 2.5 / 3 = 5/6 • gd = 2.5 / 1.5 = 5/3
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1/2
2A Y
1
2A Y
1/2
1A Y
HI-skewinverter
unskewed inverter (equal rise resistance)
unskewed inverter (equal fall resistance)
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HI- and LO-Skew � • Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition.
• Skewed gates reduce size of noncritical transistors • HI-skew gates favor rising output (small nMOS) • LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction • But larger for the other direction
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Catalog of Skewed Gates
1/2
2A Y
Inverter
1
1
22
B
AY
BA
NAND2 NOR2
1/21/2
4
4
HI-skew
LO-skew1
1A Y
2
2
11
B
AY
BA
11
2
2
gu = 5/6gd = 5/3gavg = 5/4
gu = 4/3gd = 2/3gavg = 1
gu = 1gd = 2gavg = 3/2
gu = 2gd = 1gavg = 3/2
gu = 3/2gd = 3gavg = 9/4
gu = 2gd = 1gavg = 3/2
Y
Y
1
2A Y
2
2
22
B
AY
BA
11
4
4
unskewedgu = 1gd = 1gavg = 1
gu = 4/3gd = 4/3gavg = 4/3
gu = 5/3gd = 5/3gavg = 5/3
Y
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Best P/N Ratio • We have selected P/N ratio for unit rise and fall
resistance (µ = 2-3 for an inverter). • Alternative: choose ratio for least average delay • Ex: inverter
• Delay driving identical inverter • tpdf = (P+1) • tpdr = (P+1)(µ/P) • tpd = (P+1)(1+µ/P)/2 = (P + 1 + µ + µ/P)/2 • Differentiate tpd w.r.t. P • Least delay for P = 1
PA
µ
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P/N Ratios • In general, best P/N ratio is sqrt of that giving equal
delay. • Only improves average delay slightly for inverters • But significantly decreases area and power
Inverter NAND2 NOR2
1
1.414A Y
2
2
22
B
AY
BA
11
2
2
fastestP/N ratio gu = 1.15
gd = 0.81gavg = 0.98
gu = 4/3gd = 4/3gavg = 4/3
gu = 2gd = 1gavg = 3/2
Y
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Observations • For speed:
• NAND vs. NOR • Many simple stages vs. fewer high fan-in stages • Latest-arriving input
• For area and power: • Many simple stages vs. fewer high fan-in stages
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Static CMOS logic • CMOS static characteristic • CMOS propagate delay • Large fan-in technology • CMOS power analysis
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Power consumption of combinational circuit
• Modify inverter Transistor size • Rise-fall time • Switching activity • Device thresholds and
temperature
fVCP DDLdyn2=
fVCfVCP DDLDDLdyn 102
102
→→ == α
)1( 001010 pppp −==→α
)2
1(2
0010 NN
NN−=→α
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An example of NAND
Uniform input distribution
( ) 111→0
1
-11
PPPPPP BA
=
−=
163
4341)1( 111010 ==−==→ PPPPP
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In general…
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Output transition probabilities for static logic gates