ADC: 12/14/16 BITS - 200.000 SPS PCI 150 · 2018. 10. 12. · IMB1 MBEF INTCSR MCSR CONFIGURATION...

32 entrées analogiques diff. ou 64 unifilaires

Très grande précision et faible dérive

Multiplexeurs rapides et protégés

Gains program. par logiciel de 1 à 8 en 2 n

Echantillonneur / bloqueur intégré

ADC 12/14/16 bits

Vitesse jusqu'à 200.000 acq./s

RAM double accès

Interface PCI 32 bits 33 MHz

Carte isolée galvaniquement (alimentation analogique sur la carte)

Trigger interne course libre

Format Short PCI

Support, fourniture de drivers (option)

La PCI 150 est une carte d’acquisitions analogiques. Elle permet l'acquisition de plusieurs voies (32D / 64U).

Elle est particulièrement adaptée au monde industriel et sa vitesse peut atteindre 200.000 acq./s (12 bits), 40.000 acq./s (14 bits) et 30.000 acq./s (16 bits).

Le choix de la résolution (12, 14, 16 bits) et du sur-échantillonnage permet d'adapter parfaitement le produit à l'application envisagée pour obtenir le meilleur rapport vitesse/précision.

La partie analogique de la carte est isolée galvaniquement du PCI ce qui permet de s'affranchir des retours de masse et des bruits générés par le système.

La PCI 150 offre un coût très attractif à la voie.

9 rue Georges Besse – BP 47 – 78330 FONTENAY LE FLEURY – FRANCE

Tél.:(33) 1 30 58 90 09 fax:(33) 1 30 58 21 33 http://www.adas.fr

ENTREES ANA. 32D OU 64S ADC: 12/14/16 BITS - 200.000 SPS PCI 150

PCI 150

SPÉCIFICATIONS (t = 25°C)TYPE 32 D / 64 S ENTREES ANALOGIQUES - 12 / 14 / 16 BITS -

100.000 SPS ENTREES - Nombre de voies 32 différentielles 64 entrées unifilaires - Multiplexage Statique, protégé- Niveau ± 10V FS (G = 1) - Niveau max. ± 15V sans tension appliquée; ± 35V avec tension - Impédance 1MΩ AMPLIFICAYEUR* - Gains De 1 à 8 en 2 n

- Programmation Par logiciel CONVERTISSEURS - Circuit échantillonneur/bloqueur Intégré- Résolution 12, 14 ou 16 bits - Encodage Offset binaire- Vitesse de conversion De 100,000 acq./s (12 bits) à 30,000 acq./s (16 bits) - Suréchantillonnage vitesse f(ADC) en Kéchans/s:

12 14 16 M = 1 100 40 33 M = 2 50 30 25 M = 4 33 20 20 M = 8 18 14 12.5 M = 16 8 8 8

PRECISION ± % PE 12 bits / M1 ± 0,05 % ( Σ gain + offset) 14 bits / M1 ± 0,016 % 16 bits / M1 ± 0,008 % 16 bits / M16 ± 0,002 % TRANSFERTS

interface PCI esclave ISOLEMENT GALVANIQUE

Du système (500V) ALIMENTATION - Tension + 5V / 2A ; + 3,3V / 1A CARACTERISTIQUES PHYSIQUES - Format Format Short PCI- Connecteurs face avant µD 68pts ENVIRONNEMENT- Température de fonctionnement - 20°C à + 70° C - Température de stockage - 25°C à + 85° C- Humidité relative 90 % (sans condensation) NORMES EUROPEENNES EMC - EN 61326 - EN 55011 Class A CE Compliance ROHS - 2002/95/EC

COMMENT COMMANDER? PCI 150

ACCESSOIRES - Borniers STB STB 546, STB 582- Borniers BCI BCI 184 via STB 514- Câbles WR 368

1 22/39

PCI 150 - Rev. A - Edition 2 – 23/25

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TRACEABILITY FORM

DOCUMENT FOLLOW-UP

Title: Titre : PCI 150

Documentation française Edition: 1 (Document creation - Création du document)

Revised

Approved

Written

by

by

by B. THOUËNON

M. ROCHE

D. PIMONT

on

on

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Warning: Unless otherwise stated, this revision overwrites the previous one, which must be destroyed, along with any copies given to your collaborators.

Avertissement : En l’absence d’indication contraire, cette nouvelle édition annule et remplace l’édition précédente qui doit être détruite, ainsi que les copies faites à vos collaborateurs.

Edition Edition

Nature of the modifications (key words) Nature des évolutions (mots clés)

Written Rédigé

Revised/ApprovedRevu/Approuvé

2

Séparation doc française / doc anglaise Rév. A

on

Visa

by

23/25

B. THOUËNON

on

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by

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M. ROCHE

3

on

Visa

by

on

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by

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on

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by

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on

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DOCUMENT ARCHIVEDDOCUMENT ARCHIVE No Yes on

Δ ed. .. [ ] = Document input/output (Entrée/sortie modification de la documentation) # ed. .. [ ] = Board new function input/output (Entrée/sortie nouvelle fonctionnalité du produit)

DSQ - 4.5.a - Indice F - 98/41 T.S.V.P.

PCI 150 - Rev. A - Edition 2 – 23/25

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NOTES :

!

ATTENTION

CETTE CARTE UTILISE LES ALIMENTATIONS PCI 5V ET 3,3V

PCI 150 - Rev. A - Edition 2 – 23/25

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PCI 150

SOMMAIRE

Chapitre A Présentation .........................................5

A.1. Câblage et interconnexion......................................................5

Chapitre B Interface PCI .........................................6

B.1. Avertissements........................................................................6

B.2. Littérature.................................................................................6

B.3. Registres de configuration PCI ..............................................7

B.4. Registres opérationels PCI...................................................10

Chapitre C Fonctionnement .................................12

C.1. Entrées analogiques .............................................................12

C.1.1. Entrées différentielles .................................................12

C.1.2. Entrées unifilaires .......................................................13

C.2. Multiplexage...........................................................................14

C.3. Conversion analogique digitale ...........................................15

C.4. Isolement galvanique ............................................................16

Chapitre D Registres de configuration ...............17

D.1. Introduction............................................................................17

D.2. Cartographie ..........................................................................18

D.3. Modes de fonctionnement ....................................................19

D.3.1. Mode TRIGGER .........................................................19

D.3.2. Scanning permanent...................................................19

D.4. Table des motifs ....................................................................20

D.5. Bit de fin de motif ..................................................................21

D.6. Zone de lecture des mesures ...............................................22

D.7. Les registres de configurations utilisateur.........................23

D.7.1. Registre de contrôle....................................................23 D.7.1.1. Mode SCAN ou TRIGGER....................................................................... 24

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D.7.1.2. Entrées différentielles ou unifilaires ......................................................... 24 D.7.1.3. Code de sur-échantillonnage ................................................................... 25 D.7.1.4. Nombre de bits de codage....................................................................... 25 D.7.1.5. Inversion du MSB .................................................................................... 27 D.7.1.6. Décalage du MSB (shift) .......................................................................... 27 D.7.1.7. Fin de conversion en mode TRIGGER .................................................... 27

D.7.2. Timer d’acquisitions ......................................................28

D.7.3. Start / stop ..................................................................29

Chapitre E Alimentations .....................................30

Chapitre F Mise en oeuvre ...................................31

F.1. Installation..............................................................................31

Chapitre G Entrées analogiques..........................32

G.1. Brochage en 32 entrées différentielles................................32

G.2. Brochage en 64 entrées unifilaires ......................................33

Chapitre H Borniers de conditionnement ...........34

H.1. Bornier STB 546.....................................................................34

H.2. Bornier STB 582.....................................................................34

H.3. Bornier BCI 184......................................................................34

Annexe .............................................................35

PLAN DE CONFIGURATION ...................................................................35

PLAN D’ÉQUIPEMENT ..........................................................................35

REGISTRES DE CONFIGURATION PCI.....................................................35

PCI 150 - Rev. A - Edition 2 – 23/25

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Chapitre A Présentation

La carte PCI 150 est une carte PCI d’entrées analogiques. Les points forts du produit sont : ⇒ 32 ou 64 entrées analogiques isolées du calculateur ⇒ Entrées de type instrumentation à gains programmables par logiciel ⇒ Choix de codage entre 12 et 16 bits de résolution jusqu’à 100KHz. De conception moderne et de haute technologie, la carte PCI 150 présente des caractéristiques très élevées. La carte PCI 150 s’intègre dans toutes machines répondant à la norme PCI format court.

A.1. Câblage et interconnexion

Veuillez consulter cette rubrique sur notre site Internet ou sur notre CD Rom.

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Chapitre B Interface PCI B.1. Avertissements

La carte PCI 150 est une carte qui s’insère dans un PC possédant des connecteurs PCI 32 bits. Elle présente de ce fait toutes les caractéristiques liées à cet environnement (PCI 2.1.). L’interface PCI est assurée par un composant spécialisé : AMCC S5935

B.2. Littérature

Nous recommandons vivement au lecteur de se procurer la littérature suivante :

PCI HARDWARE and SOFTWARE

Architecture et Design Written by Edward SOLARI et George WILLSE

Edit. : ANNA BOOKS

ET

AMCC PCI CONTROLLERS

S5933 DATA BOOK

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B.3. Registres de configuration PCI

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Pour la carte PCI 150, les registres sont configurés comme suit à la mise sous tension :

03 02 01 00

8850 10E8

0 0

0 0A

FFFFFFC0H

FFFFFE00H

00

FFFF0001H

00 00 01 0B

00

00

00

00

00

00

00

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

14H

10H

08H

04H

00H

D31 D0

0CH

ETAT A LA MST (Mise sous tension)

00

FF 0

PCI 150 - Rev. A - Edition 2 – 23/25 9

8850 10E8

0 0

FF 0 00 0A

FFFFFFC0H

FFFFFE00H

00

00

00

00

00

00

FFFFF0001H

00

00

00 00 01 0B

D31 D0

3CH

38H

34H

30H

2CH

28H

24H

20H

1CH

18H

10H

0CH

08H

04H

00H

64Ko

EPROM of BOOT

AMCC at Power-up

Words 16D

PCI OPERATION REGISTER

00H

Abreviations

04H

08H

0CH

10H

14H

18H

20H

24H

28H

2CH

30H

34H

38H

3CH

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

Incoming Mailbox Register 1

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

NU PCI 150

Mailbox Empty/Full status

Interrupt Control/Status Register

Bus Master Control/Status Register

IMB1

MBEF

INTCSR

MCSR

CONFIGURATION PCI 150

Words 128D PCI USER REGISTER

00H

7CH

00

PCI CONFIGURATION REGISTER

14H

80H

84H

88H

100H

104H

1F8H

1FCH

V0

V62

Reg CTL

START

STOP

Pattern 0

Pattern 1

Pattern 62

Pattern 63

V1

V63

TIMER

D31 D0

1CH

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B.4. Registres opérationels PCI

Ces 16 registres 32 bits sont accessibles via l’adresse 10H de l’espace de configuration (voir chapitre B.3. REGISTRES DE CONFIGURATION PCI).

10H FF FF FF C0

La carte PCI 150 n’utilise pas l’intégralité de ces registres mais seulement les registres suivants :

ADRESSE OFFSET ABREVIATION NOM DU REGISTRE

10H IMB1 Incoming MailBox register 1 34H MBEF MailBox Empty / Full status 38H INTCSR INTerrupt Control / Status Register 3CH MCSR Bus Master Control / Status Register

Ces registres concernent la carte dans le mode de fonctionnement esclave. Dans un but didactique, nous avons donné ci-dessus le contenu de l’ensemble des 16 registres vu du PCI.

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Le registre MCSR (3CH) Il sert à initialiser la carte PCI 150. Le bit D24 du registre positionné à « 1 » réinitialise la carte PCI 150. Le registre IMB1 (10H) Il est écrit par la carte PCI 150 lorsque la mémoire est remplie. (Ecriture dans la Mailbox 1 de la valeur FFFFFFFFH). Le registre MBEF (34H) Il s’agit du registre de status des Mailbox. Lorsque la carte PCI 150 a rempli la mémoire, elle écrit dans la Mailbox 1. Le registre MBEF passe à la valeur 000F0000H. Le fait de lire le registre IMB1 (10H) remet le registre de status MBEF à la valeur 0. Le registre INTCSR (38H) Il sert à gérer les interruptions (facultatif). La source d’interruption ne peut être que l’incoming Mailbox 1. Les bits D12 à D8 et les bits D17 à D23 sont les seuls utiles dans l’utilisation de la carte PCI 150 en mode esclave.

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Chapitre C Fonctionnement

C.1. Entrées analogiques Les entrées analogiques s'effectuent en « différentiel » ou « unifilaire » par l'intermédiaire de 1 connecteur type µD68 pts. C.1.1. Entrées différentielles >>>Chaque voie possède donc :

o Une broche entrée (+) o Une broche entrée (-) o La carte comporte 2 masses générales

Nous rappelons que "différentiel" implique "3 fils". Le montage ci-dessous illustre un câblage recommandé :

Source to measure

+

- Shielded two-wired

PCI 150

"n" channel input

+

-

Ground

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>>>La structure d'une entrée est la suivante :

Measurement amplifier CF

RF

RF

Multiplexers

IN (-)

IN (+)

Meas. ground

-

+

to Voltmeter

Où : RF + CF = Filtre d’entrée du 1er ordre

( )CFRFFc

××=

221

π

>>>Remarque : La carte PCI 150 est réalisée avec des composants CMS. Ce filtrage ne pourra donc être réalisé qu’en usine lors de la fabrication de la carte. (Sous spécifications particulières). C.1.2. Entrées unifilaires Dans le cas de l’utilisation en unifilaire de la carte, l’utilisateur bénéficie de 64 entrées. Il est à noter que ce mode d’acquisitions n’est envisageable que pour des cartes dont la conversion est sur 12 bits pour conserver la qualité des mesures. Pour des cartes 14 et 16 bits, il est préférable d’utiliser des entrées différentielles. En unifilaire, le filtrage des entrées n’est alors plus possible.

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C.2. Multiplexage

>>>Remarques :

o les entrées non utilisées doivent être reliées à la masse.

IN (+)

IN (-)

Meas. ground

Chan. X non used

o il faut être sûr que l'impédance de source est faible surtout pour les acquisitions rapides.

o les multiplexeurs sont de type "protégé" à ± 30V hors ou sous

tension.

Les voies sont présentées au convertisseur A/D via des multiplexeurs protégés 32 différentielles ou 64 unifilaires). La sélection entre différentielles et unifilaires est faite par logiciel. L’utilisateur veillera à la concordance du câblage en fonction du mode choisi. >>> NOTA : Différentiel implique 3 fils, ne pas oublier de câbler la masse

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C.3. Conversion analogique digitale

Le signal ainsi multiplexé est présenté à la chaîne suivante :

SPGA

IN (+)

IN (-)

DATA SERIE

Meas. ground

ADC

12 - 16 bits S/H

SPGA : Amplificateur à gains programmables par logiciel S/H : Echantillonneur/bloqueur ADC : Convertisseur analogique digital 12, 14 ou 16 bits La voie sélectionnée est présentée au convertisseur analogique digital de 16 bits (15 bits + signe) via l’amplificateur d’instrumentation. Le codage est en offset binaire.

VIN CODAGE H.EXA DECIMAL

+ FS - 1LSB F F F F

+ FS/2 C 0 0 0

0V 8 0 0 0

- FS/2 4 0 0 0

- FS 0 0 0 0 FS = 10,000V La résolution est de 305µV par LSB. Le convertisseur possède un échantillonneur/bloqueur intégré et sa vitesse de conversion est de 5μs. Les signaux digitaux issus de l’ADC sont transmis en série à un registre série/parallèle via des optocoupleurs

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C.4. Isolement galvanique

L'isolement galvanique dissocie les masses afin d'éviter que le bruit généré par les fonctions logiques (μP, Bus PCI, etc) ne vienne perturber les mesures de l'ADC. Dans ce cas, les parties analogiques et conversions analogiques/digitales sont séparées de la partie digitale par des photocoupleurs qui assurent cet isolement galvanique. L'alimentation analogique est elle-même isolée par un convertisseur continu / continu faible bruit.

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Chapitre D Registres de configuration

D.1. Introduction Nous avons vu dans le chapitre B « Interface PCI », la gestion de l’interface physique entre la carte PCI 150 et le bus PCI. La carte PCI 150 est décomposée en 3 « espaces » : ⇒ L’espace PCI de configuration opérationnel 10(H) ⇒ L’espace PROM de Boot 30(H) ⇒ L’espace mémoire de la carte 14(H) C’est ce dernier espace qui va être traité dans ce chapitre. Le lecteur y trouvera toutes les ressources nécessaires pour utiliser la carte PCI 150 dans les différents modes. L’espace « mémoire de la carte » se décompose en trois parties :

o La zone table des motifs o La zone de lecture des mesures analogiques o Les registres de configurations utilisateurs

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D.2. Cartographie Le tableau ci-après illustre la cartographie de la carte :

CARTOGRAPHIE PCI 150

D31 D16 D15 D0 Voie M1 Voie M0 Base (14H) +0 Voie M3 Voie M2 +4H

Voie M31 Voie M30 +3CH Voie M33 Voie M32 +40H Voie M35 Voie M34 +44H

Voie M63 Voie M62 +7CH

Timer 16 bits Reg. CTL Base +80H DUMMY START +84H DUMMY STOP +88H

Motif 0 Base +100H M1 +104H M2 +108H M31 +17CH M32 Base +180H M33 +184H M62 +1F8H M63 Base +1FCH

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D.3. Modes de fonctionnement La carte PCI 150 démarre l’acquisition par un « START » en mode scanning ou trigger. D.3.1. Mode TRIGGER Après avoir acquis 32D ou 64S voies analogiques, la PCI 150 s’arrête et les voies peuvent être lues aux adresses considérées. Une interruption peut être générée en fin de conversion. Un nouveau « START » est nécessaire pour relancer une acquisition. D.3.2. Scanning permanent Après un « START », la PCI 150 convertit en permanence les 32D ou 64S voies analogiques. Les valeurs peuvent être lues à tout moment aux adresses considérées. La PCI 150 est vue comme une mémoire double accès à rafraîchissement automatique. Dans les deux cas, un « STOP » arrête immédiatement le scanning de la carte.

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D.4. Table des motifs

La carte PCI 150 possède une table des motifs de 64 registres. Il est possible de scruter les différentes voies dans l’ordre que l’on souhaite ainsi que le nombre désiré. Cette table de 64 registres se trouve à l’adresse de base (14H) +100H, seuls les bits suivants sont utiles :

D31 D16 D15 D14 D10 D9 D8 D7 D6 D5 D0

FM CG1 CG0 Numéro de voies sur 6 bits

Les bits D0 à D5 servent à définir le numéro de la voie à scruter.

D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 Voie 0 0 0 0 0 0 1 Voie 1 0 0 0 0 1 0 Voie 2

0 1 1 1 1 1 Voie 31 1 0 0 0 0 0 Voie 32

1 1 1 1 1 0 Voie 62 1 1 1 1 1 1 Voie 63

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Chaque voie peut être amplifiée individuellement. Les deux bits de code gain adjacents à la voie permettent d’amplifier suivant le code suivant :

D9 D8 CG1 CG0 GAINS

0 0 1 0 1 2 1 0 4 1 1 8

D.5. Bit de fin de motif

Le bit D15, de chaque registre de la table des motifs, indique si une voie est à scruter après celle en conversion. Le bit D15 = 0 La fin de la table des motifs n’est pas atteinte D15 = 1 Fin de la table des motifs Lorsque la carte PCI 150 rencontre ce bit, elle scrute la voie considérée puis revient au registre 0 de la table des motifs en mode SCAN ou s’arrête en mode TRIGGER. >>> Exemple de tables de motifs : reg M0 0000 voie 0 gain 1 reg M1 0001 voie 1 gain 1 0102 voie 2 gain 2 reg Mn-1 0300 voie 0 gain 8 reg Mn 801F voie 31 gain 1 dernière voie de la table

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D.6. Zone de lecture des mesures Cet espace mémoire contient les valeurs converties. L’accès en 32 bits permet de lire 2 valeurs simultanément.

D31 D16 D15 D0

Voie M (n + 1) Voie M (n)

L’espace mémoire commence à l’adresse base +0 et peut contenir 64 voies. A l’adresse de base +0 on trouve la valeur de la voie du registre 0 de la table des motifs. En Base +2 Reg. Motif 1 Reg. Motif 2 Base +7CH Reg. Motif 62 Base +7EH Reg. Motif 63 >>>Exemple : Table des motifs

REG NUMERO VOIE

ADRESSE MESURE

VOIE MESUREE

M0 M1

M31

V0 V1

V24 +BFM

Base +0 Base +2

Base +3EH

Valeur voie 0 Valeur voie 1

Valeur voie 24

Retour Reg M0

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A la mise sous tension, la carte PCI 150 est initialisée en unipolaire 64 voies. La table des motifs est initialisée de manière à scruter 64 voies consécutives en partant de la voie 0. Reg M0 V0 Reg M1 V1 Reg M63 V63 On lira donc la valeur de la voie 0 à l’adresse Base +0 jusqu’à la valeur de la voie 63 à l’adresse Base +7EH. L’espace mémoire mesure est accessible en écriture / lecture lorsque la carte n’est pas en acquisition afin de pouvoir tester cette mémoire.

D.7. Les registres de configurations utilisateur D.7.1. Registre de contrôle Accès en lecture / écriture 16 bits à l’adresse de base (14H) +80H Ce registre permet de choisir le mode de fonctionnement de la carte.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

EOC SHT MSB BT14 BT12 MX2 MX1 MX0 DIF SC

Fin de conversion en

mode TRIGGER

Valeurs calées à droite ou à gauche en 12

et 14 bits

Inversion ou non du MSB

(complément à 2)

Type de codage 12, 14, 16 bits

Code de sur-échantillonnage

ModeSCAN

ou TRIGGER

Différentiel ou Unifilaire

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D.7.1.1. Mode SCAN ou TRIGGER

Le bit D0 permet de choisir le mode de fonctionnement de la carte PCI 150. D0 = 0 Mode SCAN (permanent après un start) D0 = 1 Mode TRIGGER (un balayage par start) >>> LE MODE SCAN Mode à la mise sous tension. Une écriture fictive à l’adresse de base +84H (start) permet de mettre la carte en acquisition permanente. Le rafraîchissement des voies se fait à la cadence du timer. >>> LE MODE TRIGGER Une écriture fictive à l’adresse de base +84H (start) lance les acquisitions, lorsque la dernière voie (motif avec le bit de fin de motif) est convertie, la carte PCI 150 s’arrête. Une nouvelle conversion des voies se fera au START suivant. Dans ce mode, un bit de fin de conversion EOC (D15) est positionné en fin de cycle ; une interruption peut aussi être émise sur le bus PCI. D.7.1.2. Entrées différentielles ou unifilaires

Le bit D1 permet de sélectionner le type d’entrées analogiques soit différentiel soit unifilaire. D1 = 0 Entrées unifilaires (64 max.) D1 = 1 Entrées différentielles (32 max.)

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D.7.1.3. Code de sur-échantillonnage

Les bits D4, D5, D6 permettent de choisir ou non un sur-échantillonnage.

D6 MX2

D5 MX1

D4 MX0

SUR-ECHANTILLONNAGE

0 0 0 Pas de sur-échantillonnage (M1)0 0 1 X 2 (M2) 0 1 0 X 4 (M4) 0 1 1 X 8 (M8) 1 X X X 16 (M16)

Les différentes vitesses d’échantillonnage sont liées au nombre de bits utilisés et au sur-échantillonnage (voir ci-dessous). D.7.1.4. Nombre de bits de codage

Les bits D8 et D9 permettent de choisir le nombre de bits utilisés par la carte PCI 150. Choix du 12 / 14 / 16 bits

CODAGE D9 D8 12 bits 0 1 14 bits 1 0 16 bits 0 0

Le code 11 est réservé

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Interaction entre le sur-échantillonnage et le nombre de bits de codage >>>Codage 12 bits

Sur- échantillonnage Vitesse maximale d’échantillonnage

M1 100K/s M2 50K/s M4 33K/s M8 18K/s

M16 8K/s >>>Codage 14 bits


M1 40K/s M2 30K/s M4 20K/s M8 14K/s

M16 8K/s >>>Codage 16 bits


M1 33K/s M2 25K/s M4 20K/s M8 12,5K/s

M16 8K/s

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D.7.1.5. Inversion du MSB

Le bit D10 permet de choisir le signe du MSB D10 = 0 ⇒ MSB (codage binaire) D10 = 1 ⇒ MSB inversé (complément à deux) D.7.1.6. Décalage du MSB (shift)

En 12 et 14 bits, on peut aligner le poids fort sur le MSB en positionnant ce bit à 1 D11 = 0 ⇒ LSB sur D0 D11 = 1 ⇒ MSB sur D15 D.7.1.7. Fin de conversion en mode TRIGGER

Le bit D15 permet de connaître l’état de la carte PCI 150 EOC =

En mode TRIGGER, le bit D15 passe à « 1 » en fin de conversion des voies définies dans la table des motifs. Le fait de lire le registre « clear » le bit. >>>Nota : En mode SCAN, EOC est toujours à zéro

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D.7.2. Timer d’acquisitions Accès en lecture / écriture 16 bits à l’adresse de base (14H) +82H La fréquence d’échantillonnage de l’ensemble des voies est fournie par ce timer en mode SCAN.

D15 D0

Valeur du timer 16 bits

La valeur du timer n est comprise en 1 ≤ n ≤ 65535 La fréquence d’échantillonnage est égale à

1200

+nKHz

Soit une fréquence d’échantillonnage de voies comprise entre 3Hz < Fe ≤ 100KHz Ce timer cadence la vitesse d’acquisition des blocs de voies définies dans la table de motifs. >>>Exemple 1 : 64 voies unifilaires à vitesse maximale (pas d’oversampling, gain de 1, 12 bits) Temps de scrutation de chaque voie 10µs Le timer peut être activé toutes les 640µs Soit n = 127 (décimal) >>>Exemple 2 : 32 voies différentielles avec oversampling x 16 Codage 16 bits (précision maximale) Temps de scrutation de chaque voie 125µs Le timer sera activé toutes les 125 x 32 = 4ms Soit n = 799 (décimal)

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D.7.3. Start / stop Ils sont situés aux adresses base + 84H et base + 88H Accès en écriture de ces deux adresses. Une écriture « fictive » déclenche : Base + 84H = START Base + 88H = STOP >>>Nota :

Un START est nécessaire à l’initialisation pour lancer les acquisitions quel que soit le mode SCAN ou TRIGGER.

Un STOP arrête immédiatement les acquisitions.

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Chapitre E Alimentations

La carte PCI 150 nécessite du + 3,3V/1A et + 5V/2A issus du bus PCI. Elle génère par l'intermédiaire d'un convertisseur continu / continu les tensions ± 15V nécessaires pour la partie analogique.

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Chapitre F Mise en oeuvre F.1. Installation

La carte PCI 150 devra être installée dans un châssis PCI. Elle utilise un slot court. Les cartes doivent être enlevées ou insérées dans le châssis hors tension. Veiller aux problèmes d'électricité statique lorsque la carte est sortie de son sachet antistatique. L’utilisateur consultera le document :

GENERAL INSTRUCTIONS FOR IMPLEMENTING ADAS PRODUCTS

INSTRUCTIONS GENERALES DE MISE EN OEUVRE DES PRODUITS ADAS

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Chapitre G Entrées analogiques

Les entrées s’effectuent par 1 connecteur µD 68 pts. G.1. Brochage en 32 entrées différentielles

BROCHE SIGNAL BROCHE SIGNAL

1 35 0V-MES

2 VOIE 0- 36 VOIE 0+








10 VOIE 8- 44 VOIE 8+

11 VOIE 9- 45 VOIE 9+

12 VOIE 10- 46 VOIE 10+

13 VOIE 11- 47 VOIE 11+

14 VOIE 12- 48 VOIE 12+

15 VOIE 13- 49 VOIE 13+

16 VOIE 14- 50 VOIE 14+

17 VOIE 15- 51 VOIE 15+

18 VOIE 16- 52 VOIE 16+

19 VOIE 17- 53 VOIE 17+

20 VOIE 18- 54 VOIE 18+

21 VOIE 19- 55 VOIE 19+

22 VOIE 20- 56 VOIE 20+

23 VOIE 21- 57 VOIE 21+

24 VOIE 22- 58 VOIE 22+

25 VOIE 23- 59 VOIE 23+

26 VOIE 24- 60 VOIE 24+

27 VOIE 25- 61 VOIE 25+

28 VOIE 26- 62 VOIE 26+

29 VOIE 27- 63 VOIE 27+

30 VOIE 28- 64 VOIE 28+

31 VOIE 29- 65 VOIE 29+

32 VOIE 30- 66 VOIE 30+

33 VOIE 31- 67 VOIE 31+

34 0V_MES 68

µD 68S

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G.2. Brochage en 64 entrées unifilaires

µD 68S

BROCHE SIGNAL BROCHE SIGNAL

1 35 0V_MES

2 VOIE 0 36 VOIE 16

3 VOIE 1 37 VOIE 17

4 VOIE 2 38 VOIE 18

5 VOIE 3 39 VOIE 19

6 VOIE 4 40 VOIE 20

7 VOIE 5 41 VOIE 21

8 VOIE 6 42 VOIE 22

9 VOIE 7 43 VOIE 23

10 VOIE 8 44 VOIE 24

11 VOIE 9 45 VOIE 25

12 VOIE 10 46 VOIE 26

13 VOIE 11 47 VOIE 27

14 VOIE 12 48 VOIE 28

15 VOIE 13 49 VOIE 29

16 VOIE 14 50 VOIE 30

17 VOIE 15 51 VOIE 31

18 VOIE 32 52 VOIE 48

19 VOIE 33 53 VOIE 49

20 VOIE 34 54 VOIE 50

21 VOIE 35 55 VOIE 51

22 VOIE 36 56 VOIE 52

23 VOIE 37 57 VOIE 53

24 VOIE 38 58 VOIE 54

25 VOIE 39 59 VOIE 55

26 VOIE 40 60 VOIE 56

27 VOIE 41 61 VOIE 57

28 VOIE 42 62 VOIE 58

29 VOIE 43 63 VOIE 59

30 VOIE 44 64 VOIE 60

31 VOIE 45 65 VOIE 61

32 VOIE 46 66 VOIE 62

33 VOIE 47 67 VOIE 63

34 0V_MES 68

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Chapitre H Borniers de conditionnement

La carte PCI 150 s’inscrit dans une offre globale d’acquisitions proposée par ADAS. Elle peut donc être reliée à des borniers de raccordement.

H.1. Bornier STB 546

Le bornier STB 546 permet le câblage direct fil à fil des entrées analogiques unifilaires ou différentielles.

H.2. Bornier STB 582

o Si l’utilisateur souhaite des entrées isolées entre elles et vis-à-vis du calculateur

o Si l’utilisateur souhaite conditionner des tensions, boucles de courant, thermocouples, PT100, potentiomètres, etc...

⇒ Le bornier STB 582 assure ces fonctionnalités. Il se « clips » sur

RAIL DIN.

H.3. Bornier BCI 184

o Si l’utilisateur souhaite des entrées isolées entre elles et vis-à-vis du calculateur

o Si l’utilisateur souhaite conditionner des tensions, boucles de courant, thermocouples, PT 100, potentiomètres, etc ...

⇒ Le bornier BCI 184 assure ces fonctionnalités. Il se présente au

format Double Europe/6Te

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Annexe

PLAN DE CONFIGURATION

PLAN D’EQUIPEMENT

REGISTRES DE CONFIGURATION PCI

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NOTE AU LECTEUR Ce chapitre est laissé volontairement en anglais afin de garder les termes utilisés dans la norme PCI.

Configuration Abbreviation Register NameAddress Offset

00h–01h VID Vendor Identification02h–03h DID Device Identification04h–05h PCICMD PCI Command Register06h–07h PCISTS PCI Status Register08h RID Revision Identification Register09h–0Bh CLCD Class Code Register0Ch CALN Cache Line Size Register0Dh LAT Master Latency Timer0Eh HDR Header Type0Fh BIST Built-in Self-test10h–27h BADR0-BADR5 Base Address Registers (0-5)28h–2Fh — Reserved30h EXROM Expansion ROM Base Address34h–3Bh — Reserved3Ch INTLN Interrupt Line3Dh INTPIN Interrupt Pin3Eh MINGNT Minimum Grant3Fh MAXLAT Maximum Latency40h–FFh — Not used

PCI CONFIGURATION REGISTERSEach PCI bus device contains a unique 256-byte region called its configuration header space. Portions of thisconfiguration header are mandatory in order for a PCI agent to be in full compliance with the PCI specification.This section describes each of the configuration space fields—its address, default values, initialization options,and bit definitions—and also provides an explanation of its intended usage.

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VENDOR IDENTIFICATION REGISTER (VID)Register Name: Vendor IdentificationAddress Offset: 00h-01hPower-up value: 10E8h (AMCC, Applied Micro

Circuits Corp.)Boot-load: External nvRAM offset

040h-41hAttribute: Read Only (RO)Size: 16 bits

The VID register contains the vendor identificationnumber. This number is assigned by the PCI SpecialInterest Group and is intended to uniquely identifyany PCI device. Write operations from the PCI inter-face have no effect on this register. After reset isremoved, this field can be boot-loaded from the ex-ternal non-volatile device (if present and valid) so thatother legitimate PCI SIG members can substitute theirvendor identification number for this field.

Bit Description

15 010E8h

Vendor Identification Register (RO)

15:0 Vendor Identification Number: This is a 16 bit-value assigned to AMCC.

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PCI CONFIGURATION REGISTERS

DEVICE IDENTIFICATION REGISTER (DID) Register Name: Device Identification Address Offset: 02h-03h Power-up value: 4750h (ASCII hex for ‘GP’,

General Purpose) Boot-load: External nvRAM offset

042h-43hAttribute: Read OnlySize: 16 bits

15 0

Device Identification Register (RO)

8850

Bit Description

15:0 Device Identification Number: This is a 16-bit value initially assigned by AMCC to ADAS applications for PCI 150 card.

The DID register contains the vendor-assigned deviseidentification number. This number is generated by AMCCin compliance with the conditions of the PCI specification.Write operations from the PCI interface have no effect onthis register. After reset is removed, this field can be boot-loaded from the external non-volatile device (if present andvalid) so that other legitimate PCI SIG members cansubstitute their own device identification number for thisfield.

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PCI COMMAND REGISTERRegister Name: PCI CommandAddress Offset: 04h-05hPower-up value: 0000hBoot-load: not usedAttribute: Read/Write (R/W on 6 bits,

Only for all others)Size: 16 bits

This 16-bit register contains the PCI Command. Thefunction of this register is defined by the PCI specifi-cation and its implementation is required of all PCIdevices. Only six of the ten fields are used by thisdevice; those which are not used are hardwired to 0.The definitions for all fields are provided here forcompleteness.

15 0

Reserved = 00's

Fast Back-to-BackSERREWait Cycle EnableParity Error EnablePalette SnoopMemory Write and InvalidateSpecial Cycle EnableBus Master EnableMemory AccessI/O Access Enable

X 00 X 0 0 0 XXX

123456789

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15:10 Reserved. Equals all 0’s.

9 Fast Back-to-Back Enable. The S5933 does not support this function. This bit must be set to zero.This bit is cleared to a 0 upon RESET#.

8 System Error Enable. When this bit is set to 1, it permits the S5933 controller to drive the open drainoutput pin, SERR#. This bit is cleared to 0 upon RESET#. The SERR# pin driven active normallysignifies a parity error on the address/control bus.

7 Wait Cycle Enable. This bit controls whether this device does address/data stepping. Since the S5933controller never uses stepping, it is hardwired to 0.

6 Parity Error Enable. This bit, when set to a one, allows this controller to check for parity errors. Whena parity error is detected, the PCI bus signal PERR# is asserted. This bit is cleared (parity testingdisabled) upon the assertion of RESET#.

5 Palette Snoop Enable. This bit is not supported by the S5933 controller and is hardwired to 0. Thisfeature is used solely for PCI-based VGA devices.

4 Memory Write and Invalidate Enable. This bit allows certain Bus Master devices to use the MemoryWrite and Invalidate PCI bus command when set to 1. When set to 0, masters must use the MemoryWrite command instead. The S5933 controller does not support this command when operated as amaster and therefore it is hardwired to 0.

3 Special Cycle Enable. Devices which are capable of monitoring special cycles can do so when thisbit is set to 1. The S5933 controller does not monitor (or generate) special cycles and this bit ishardwired to 0.

2 Bus Master Enable. This bit, when set to a one, allows the S5933 controller to function as a bus master.This bit is initialized to 0 upon the assertion of signal pin RESET#.

1 Memory Space Enable. This bit allows the S5933 controller to decode and respond as a target formemory regions that may be defined in one of the five base address registers. This bit is initializedto 0 upon the assertion of signal pin RESET#.

0 I/O Space Enable. This bit allows the S5933 controller to decode and respond as a target to I/O cycleswhich are to regions defined by any one of the five base address registers. This bit is initialized to 0upon the assertion of signal pin RESET#.

Bit Description

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PCI STATUS REGISTER (PCISTS)

Register Name: PCI Status

Address Offset: 06h-07h

Power-up value: 0080hBoot-load: not usedAttribute: Read Only (RO), Read/Write

Clear (R/WC)Size: 16 bits

7 0

X00XXX

6

XX

Reserved (RO)

Signaled Target Abort (R/WC)Received Target Abort (R/WC)Received Master Abort (R/WC)Signaled System Error (R/WC)Detected Parity Error (R/WC)

0

15 14 13 12 11 10 9 8

Reserved (RO) = 00's

Fast Back-to-Back (RO)Data Parity Reported (R/WC)

DEVSEL# Timing Status (RO) 0 0 = Fast (S5933) 0 1 = Medium 1 0 = Slow 1 1 = Reserved

This 16-bit register contains the PCI status informa-tion. The function of this register is defined by thePCI specification and its implementation is requiredof all PCI devices. Only some of the bits are used bythis device; those which are not used are hardwiredto 0. Most status bits within this register are desig-nated as “write clear,” meaning that in order to cleara given bit, the bit must be written as a 1. All bitswritten with a 0 are left unchanged. These bits areidentified in Figure 4 as (R/WC). Those which areRead Only are shown as (RO) in Figure 4.

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Bit Description

15 Detected Parity Error. This bit is set whenever a parity error is detected. It functions independentlyfrom the state of Command Register Bit 6. This bit may be cleared by writing a 1 to this location.

14 Signaled System Error. This bit is set whenever the device asserts the signal SERR#. This bit can bereset by writing a 1 to this location.

13 Received Master Abort. This bit is set whenever a bus master abort occurs. This bit can be reset bywriting a 1 to this location.

12 Received Target Abort. This bit is set whenever this device has one of its own initiated cyclesterminated by the currently addressed target. This bit can be reset by writing a 1 to this location.

11 Signaled Target Abort. This bit is set whenever this device aborts a cycle when addressed as a target.This bit can be reset by writing a 1 to this location.

10:9 Device Select Timing. These bits are read-only and define the signal behavior of DEVSEL# from thisdevice when accessed as a target.

8 Data Parity Reported. This bit is set upon the detection of a data parity error for a transfer involvingthe S5933 device as the master. The Parity Error Enable bit (D6 of the Command Register) must beset in order for this bit to be set. Once set, it can only be cleared by either writing a 1 to this locationor by the assertion of the signal RESET#.

7 Fast Back-to-back Capable. When equal to 1, this indicates that the device can accept fast back-to-back cycles as a target.

6:0 Reserved. Equal all 0’s.

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REVISION IDENTIFICATION REGISTER (RID)Register Name: Revision IdentificationAddress Offset: 08hPower-up value: 00hBoot-load: External nvRAM/EPROM offset

048hAttribute: Read OnlySize: 8 bits

The RID register contains the revision identificationnumber. This field is initially cleared. Write operationsfrom the PCI interface have no effect on this register.After reset is removed, this field can be boot-loadedfrom the external non-volatile device (if present andvalid) so that another value may be used.

Bit Description

7:0 Revision Identification Number. Initialized to zeros, this register may be loaded to the value in non-volatile memory at offset 048h.

7 000h

Revision Identification Number (RO)

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CLASS CODE REGISTER (CLCD)Register Name: Class CodeAddress Offset: 09h-0BhPower-up value: FF0000hBoot-load: External nvRAM offset

049h-4BhAttribute: Read OnlySize: 24 bits

This 24-bit, read-only register is divided into threeone-byte fields: the base class resides at location0Bh, the sub-class at 0Ah, and the programming in-terface at 09h. The default setting for the base classis all ones (FFh), which indicates that the devicedoes not fit into the thirteen base classes defined inthe PCI Local Bus Specification. It is possible, how-ever, through use of the external non-volatilememory, to implement one of the defined class codesdescribed in Table 7 below.

For devices that fall within the seven defined classcodes, sub-classes are also assigned. Tables 8through 20 describe each of the sub-class codes forbase codes 00h through 0Ch, respectively.

7 0Sub-Class

7070Base Class Prog I/F

(Bit)(Offset)@09h@0Ah@0Bh

Base-Class Description

00h Early, pre-2.0 PCI specification devices

01h Mass storage controller

02h Network controller

03h Display controller

04h Multimedia device

05h Memory controller

06h Bridge device

07h Simple communication controller

08h Base system peripherals

09h Input devices

0Ah Docking stations

0Bh Processors

0Ch Serial bus controllers

0D-FEh Reserved

FFh Device does not fit defined class codes (default)

Sub-Class Prog I/F Description

00h 00h All devices other than VGA

01h 00h VGA-compatible device

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45


00h 00h RAM memory controller

01h 00h Flash memory controller

80h 00h Other memory controller


00h 00h SCSI controller

01h xxh IDE controller

02h 00h Floppy disk controller

03h 00h IPI controller

04h 00h RAID controller

80h 00h Other mass storage controller


00h 00h Ethernet controller

01h 00h Token ring controller

02h 00h FDDI controller

03h 00h ATM controller

80h 00h Other network controller


00h 00h VGA-compatible controller

00h 01h 8514 compatible controller

01h 00h XGA controller

80h 00h Other display controller


00h 00h Video device

01h 00h Audio device

80h 00h Other multimedia device

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46


00h 00h Host/PCI bridge

01h 00h PCI/ISA bridge

02h 00h PCI/EISA bridge

03h 00h PCI/Micro Channel bridge

04h 00h PCI/PCI bridge

05h 00h PCI/PCMCIA bridge

06h 00h NuBus bridge

07h 00h CardBus bridge

80h 00h Other bridge type


00h 00h Generic XT compatible serial controller

01h 16450 compatible serial controller

02h 16550 compatible serial controller

01h 00h Parallel port

01h Bidirectional parallel port

02h ECP 1.X compliant parallel port

80h 00h Other communications device


00h 00h Generic 8259 PIC

01h ISA PIC

02h EISA PIC

01h 00h Generic 8237 DMA controller

01h ISA DMA controller

02h EISA DMA controller

02h 00h Generic 8254 system timer

01h ISA system timer

02h EISA system timers (2 timers)

03h 00h Generic RTC controller

01h ISA RTC controller

80h 00h Other system peripheral

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00h 00h Keyboard controller

01h 00h Digitizer (Pen)

02h 00h Mouse controller

80h 00h Other input controller


00h 00h Generic docking station

80h 00h Other type of docking station


00h 00h Intel386™

01h 00h Intel486™

02h 00h Pentium™

10h 00h Alpha™

40h 00h Co-processor


00 00h FireWire™ (IEEE 1394)

01h 00h ACCESS.bus

02h 00h SSA

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CACHE LINE SIZE REGISTER (CALN)Register Name: Cache Line SizeAddress Offset: 0ChPower-up value: 00h, hardwiredBoot-load: not usedAttribute: Read OnlySize: 8 bits

This register is hardwired to 0. The cache line con-figuration register is used by the system to define thecache line size in doubleword (64-bit) increments.This controller does not use the “Memory Write andInvalidate” PCI bus cycle commands when operatingin the bus master mode, and therefore does not inter-nally require this register. When operating in the tar-get mode, this controller does not have theconnections necessary to “snoop” the PCI bus andaccordingly cannot employ this register in the detec-tion of burst transfers that cross a line boundary.

7 000h

Cache Line Size (RO)

LATENCY TIMER REGISTER (LAT)Register Name: Latency TimerAddress Offset: 0DhPower-up value: 00hBoot-load: External nvRAM offset

04DhAttribute: Read/Write, bits 7:3;

Read Only bits 2:0Size: 8 bits

The latency timer register has meaning only whenthis controller is used as a bus master and pertains tothe number of PCI bus clocks that this master will beguaranteed. The nonzero value for this register isinternally decremented after this device has beengranted the bus and has begun to assert FRAME#.Prior to this latency timer count reaching zero, thisdevice can ignore the removal of the bus grant andmay continue the use of the bus for data transfers.

7 0

Latency Timer value (R/W)# of clocks x 8

0

1

0

2

0

3

X

4

X

5

X

6

XX

Bit

Value

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HEADER TYPE REGISTER (HDR)Register Name: Header TypeAddress Offset: 0EhPower-up value: 00hBoot-load: External nvRAM offset

04EhAttribute: Read OnlySize: 8 bits

This register consists of two fields: Bits 6:0 define theformat for bytes 10h through 3Fh of the device con-figuration header, and bit 7 establishes whether thisdevice represents a single function (bit 7 = 0) or amultifunction (bit 7 = 1) PCI bus agent. The S5933 isa single function PCI device.

7 0

Single/Multi-function device (Read Only)0 = single function1 = multi-function

123456

X

Bit

Value00h

Format field (Read Only)

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BUILT-IN SELF-TEST REGISTER (BIST)Register Name: Built-in Self-TestAddress Offset: 0FhPower-up value: 00hBoot-load: External nvRAM/EPROM

offset 04FhAttribute: D7, D5-0 Read Only, D6 as

PCI bus write onlySize: 8 bits

The Built-In Self-Test (BIST) register permits theimplementation of custom, user-specific diagnostics.This register has four fields as depicted in Figure 10.Bit 7, when set signifies that this device supports abuilt-in self test. When bit 7 is set, writing a 1 to bit 6will commence the self test. In actuality, writing a 1 tobit 6 produces an interrupt to the Add-On interface.Bit 6 will remain set until cleared by a write operationto this register from the Add-On bus interface. Whenbit 6 is reset it is interpreted as completion of the self-test and an error is indicated by a non-zero value forthe completion code (bits 3:0).

Bit Description

7 BIST Capable. This bit indicates that the Add-On device supports a built-in self-test when a one isreturned. A zero should be returned if this self test feature is not desired. This field is read onlyfrom the PCI interface.

6 Start BIST. Writing a 1 to this bit indicates that the self-test should commence. This bit can only bewritten when bit 7 is a 1. When bit 6 becomes set, an interrupt is issued to the Add-On interface. Otherthan through the reset pin, Bit 6 can only be cleared by a write to this element from the Add-On businterface as outlined in Section 6.5. The PCI bus specification requires that this bit be cleared within2 seconds after being set, or the device will be failed.

5:4 Reserved. These bits are reserved. This field will always return zeros.

3:0 Completion Code. This field provides a method for detailing a device-specific error. It is consideredvalid when the Start BIST field (bit 6) changes from 1 to 0. An all-zero value for the completion codeindicates successful completion.

7 0

X

1

X

2

X

3

X

4

0

5

0

6

0X

Bit

Value

User definedCompletion Code (RO)

Reserved (RO)

Start BIST (WO)

BIST Capable (RO)

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BASE ADDRESS REGISTERS (BADR)Register Name: Base AddressAddress Offset: 10h, 14h, 18h, 1Ch, 20h, 24hPower-up value: FFFFFFC1h for offset 10h;

00000000h for all othersBoot-load: External nvRAM offset

050h, 54h, 58h, 5Ch, 60h(BADR0-4)

Attribute: high bits Read/Write; low bitsRead Only

Size: 32 bits

The base address registers provide a mechanism forassigning memory or I/O space for the Add-On func-tion. The actual location(s) the Add-On function is torespond to is determined by first interrogating theseregisters to ascertain the size or space desired, andthen writing the high-order field of each register toplace it physically in the system’s address space. Bitzero of each field is used to select whether the spacerequired is to be decoded as memory (bit 0 = 0) or I/O(bit 0 = 1). Since this PCI controller has 16 DWORDsof internal operating registers, the Base AddressRegister at offset 10h is assigned to them. The re-maining five base address registers can only be usedby boot-loading them from the external nvRAM inter-face. BADR5 register is not implemented and will re-turn all 0’s.

Determining Base Address SizeThe address space defined by a given base addressregister is determined by writing all 1s to a givenbase address register from the PCI bus and thenreading that register back. The number of 0s returnedstarting from D4 for memory space and D2 for I/Ospace toward the high-order bits reveals the amountof address space desired. Tables 23 and 24 list thepossible returned values and their corresponding sizefor both memory and I/O, respectively. Included inthe table are the nvRAM/EPROM boot values whichcorrespond to a given assigned size. A register re-turning all zeros is disabled.

Assigning the Base Address

After a base address has been sized as described inthe preceding paragraph, the region associated withthat base address register (the high order one bits)can physically locate it in memory (or I/O) space. Forexample, the first base address register returnsFFFFFFC1h indicating an I/O space (D0=1) and isthen written with the value 00000300h. This meansthat the controller’s internal registers can be selectedfor I/O addresses between 00000300h through0000033Fh, in this example. The base address valuemust be on a natural binary boundary for the requiredsize (example 300h, 340h, 380h etc.; 338h would notbe allowable).

31 0

X

1

0

2 Bit

Value

I/O Space Indicator (RO)Reserved (RO)

Programmable (R/W)

31 0

X

1

X

2

X

3

X

4 Bit

Value

Memory Space Indicator (RO)Type (RO) 00-locate anywhere (32) 01-below 1 MB 10-locate anywhere (64) 11-reserved

Programmable (R/W)

Prefetchable (RO)

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31:4 Base Address Location. These bits are used to position the decoded region in memory space. Onlybits which return a 1 after being written as 1 are usable for this purpose. Except for Base AddressRegister 0, these bits are individually enabled by the contents sourced from the external boot memory.

3 Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachableregions can only be located within the region altered through PCI bus memory writes. This bit, whenset, also implies that all read operations will return the data associated for all bytes regardless of theByte Enables. Memory space which cannot support this behavior should leave this bit in the zerostate. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by theexternal boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is readonly from the PCI interface.

2:1 Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the spacelocation is restricted to be within the first megabyte of memory space. The table below describes theencoding:

Bits Description2 10 0 Region is 32 bits wide and can be located anywhere in 32 bit memory space.

0 1 Region is 32 bits wide and must be mapped below the first MByte of memory space.

1 0 Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.(Not supported by this controller.)

1 1 Reserved. (Not supported by this controller.)

1 The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The onlymeaningful option is whether it is desired to position memory space anywhere within 32-bit memoryspace or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the resetpin and later initialized by the external boot memory (if present).

0 Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space andthe remaining bits in the base address register are defined as shown in Table 22a.

Bit Description

Bit Description

31:2 Base Address Location. These bits are used to position the decoded region in I/O space. Only bitswhich return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,these bits are individually enabled by the contents sourced from the external boot memory (EPROMor nvRAM).

1 Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for theentire register location, bits 31 through 0).

0 Space Indicator = 1. When one this bit identifies a base address region as an I/O space and theremaining bits in the base address register have the definition as shown in Table 11b.

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Response Size in bytes [EPROM boot value] 1

00000000h none - disabled 00000000h orBIOS missing 2,3

FFFFFFF0h 16 bytes (4 DWORDs) FFFFFFF0h

FFFFFFE0h 32 bytes (8 DWORDs) FFFFFFE0h

FFFFFFC0h 64 bytes (16 DWORDs) FFFFFFC0h

FFFFFF80h 128 bytes (32 DWORDs) FFFFFF80h


FFFFFE00h 512 bytes (128 DWORDs) FFFFFE00h

FFFFFC00h 1K bytes (256 DWORDs) FFFFFC00h

FFFFF800h 2K bytes (512 DWORDs) FFFFF800h

FFFFF000h 4K bytes (1K DWORDs) FFFFF000h

FFFFE000h 8K bytes (2K DWORDs) FFFFE000h

FFFFC000h 16K bytes (4K DWORDs) FFFFC000h

FFFF8000h 32K bytes (8K DWORDs) FFFF8000h


FFFE0000h 128K bytes (32K DWORDs) FFFE0000h

FFFC0000h 256K bytes (64K DWORDs) FFFC0000h

FFF80000h 512K bytes (128K DWORDs) FFF80000h

FFF00000h 1M bytes (256K DWORDs) FFF00000h

FFE00000h 2M bytes (512K DWORDs) FFE00000h

FFC00000h 4M bytes (1M DWORDs) FFC00000h

FF800000h 8M bytes (2M DWORDs) FF800000h

FF000000h 16M bytes (4M DWORDs) FF000000h

FE000000h 32M bytes (8M DWORDs) FE000000h

FC000000h 64M bytes (16M DWORDs) FC000000h

F8000000h 128M bytes (32M DWORDs) F8000000h

F0000000h 256M bytes (64M DWORDs) F0000000h

E0000000h 512M bytes (128M DWORDs) E0000000h

1. The two most significant bits define bus width for BADR1:4 in Pass-Thru operation).2. Bits D3, D2 and D1 may be set to indicate other attributes for the memory space. See text for details.3. BADR5 register is not implemented and will return all 0’s.

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Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing 3

FFFFFFFDh 4 bytes (1 DWORDs) FFFFFFFDh



FFFFFFE1h 32 bytes (8 DWORDs) FFFFFFE1h

FFFFFFC1h 64 bytes (16 DWORDs) FFFFFFC1h 4



4. Base Address Register 0 (at offset) 10h powers up as FFFFFFC1h. This default assignment allows usage without an external bootmemory. Should an EPROM or nvRAM be used, the base address can be boot loaded to become a memory space (FFFFFFC0h orFFFFFFC2h).

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EXPANSION ROM BASE ADDRESSREGISTER (XROM)

Register Name: Expansion ROM Base AddressAddress Offset: 30hPower-up value: 00000000hBoot-load: External nvRAM offset

70hAttribute: bits 31:11, bit 0 Read/Write; bits

10:1 Read OnlySize: 32 bits

31 0

00

110 Bit

Value

Address Decode Enable (RW) 0=Disabled 1=EnabledReserved (RO)Programmable (R/W)

11

The expansion base address ROM register providesa mechanism for assigning a space within physicalmemory for an expansion ROM. Access from the PCIbus to the memory space defined by this register willcause one or more accesses to the S5933 control-lers’ external BIOS ROM (or nvRAM) interface. SincePCI bus accesses to the ROM may be 32 bits wide,repeated operations to the ROM are generated bythe S5933 and the wider data is assembled internalto the S5933 controller and then transferred to thePCI bus by the S5933.

Bit Description

31:11 Expansion ROM Base Address Location. These bits are used to position the decoded region inmemory space. Only bits which return a 1 after being written as 1 are usable for this purpose. Thesebits are individually enabled by the contents sourced from the external boot memory (EPROM ornvRAM). The desired size for the ROM memory is determined by writing all ones to this register andthen reading back the contents. The number of bits returned as zeros, in order from least significantto most significant bit, indicates the size of the expansion ROM. This controller limits the expansionROM area to 64K bytes. The allowable returned values after all ones are written to this register areshown in Table 26.

10:1 Reserved. All zeros.

0 Address Decode Enable. The Expansion ROM address decoder is enabled or disabled with this bit.When this bit is set, the decoder is enabled; when this bit is zero, the decoder is disabled. It is requiredthat the PCI command register also have the memory decode enabled for this bit to have an effect.

Response Size in bytes [EPROM boot value]00000000h none - disabled 00000000h or

BIOS missing

FFFFF801h 2K bytes (512 DWORDs) FFFFF801h

FFFFF001h 4K bytes (1K DWORDs) FFFFF001h

FFFFE001h 8K bytes (2K DWORDs) FFFFE001h

FFFFC001h 16K bytes (4K DWORDs) FFFFC001h



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INTERRUPT LINE REGISTER (INTLN)Register Name: Interrupt LineAddress Offset: 3ChPower-up value: FFhBoot-load: External nvRAM offset

7ChAttribute: Read/WriteSize: 8 bit

This register indicates the interrupt routing for theS5933 controller. The ultimate value for this registeris system-architecture specific. For x86 based PCs,the values in this register correspond with the estab-lished interrupt numbers associated with the dual8259 controllers used in those machines. In x86-based PC systems, the values of 0 to 15 correspondwith the IRQ numbers 0 through 15, and the valuesfrom 16 to 254 are reserved. The value of 255 (thecontroller’s default power-up value) signifies either“unknown” or “no connection” for the system inter-rupt. This register is boot-loaded from the externalboot memory, if present, and may be written by thePCI interface.

7 01

FFh

5 Bit

Value

6 4 23

INTERRUPT PIN REGISTER (INTPIN)Register Name: Interrupt PinAddress Offset: 3DhPower-up value: 01hBoot-load: External nvRAM offset

7DhAttribute: Read OnlySize: 8 bits

7 015 Bit

Value

6 4 23

0 0000 XXX

Reserved (all zeroes-RO)

Pin Number 0 0 0 None0 0 1 INTA#0 1 0 INTB#0 1 1 INTC#1 0 0 INTD# 1 0 1 Reserved1 1 X Reserved

This register identifies which PCI interrupt, if any, isconnected to the controller’s PCI interrupt pins. Theallowable values are 0 (no interrupts), 1 (INTA#), 2(INTB#), 3 (INTC#), and 4 (INTD#). The defaultpower-up value assumes INTA#.

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MINIMUM GRANT REGISTER (MINGNT)Register Name: Minimum Grant

Address Offset: 3EhPower-up value: 00hBoot-load: External nvRAM offset

7EhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how long a burst period the device needs.A value of zero indicates that the bus master has nostringent requirement. The units defined by the leastsignificant bit are in 250-ns increments. This registeris treated as “information only” and has no furtherimplementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

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MAXIMUM LATENCY REGISTER (MAXLAT)

Register Name: Maximum LatencyAddress Offset: 3FhPower-up value: 00hBoot-load: External nvRAM offset

7FhAttribute: Read OnlySize: 8 bits

This register may be optionally used by bus mastersto specify how often this device needs PCI bus ac-cess. A value of zero indicates that the bus masterhas no stringent requirement. The units defined bythe least significant bit are in 250-ns increments. Thisregister is treated as “information only” and has nofurther implementation within this device.

Values other than zero are possible when an externalboot memory is used.

7 0

Value x 250ns (RO)00-no requirement01-FFh

123456

0

bit

value0 0 0 0 0 0 0

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PCI BUS OPERATION REGISTERS

Address Offset Abbreviation Register Name

00h OMB1 Outgoing Mailbox Register 1



0Ch OMB4 Outgoing Mailbox Register 4

10h IMB1 Incoming Mailbox Register 1



1Ch IMB4 Incoming Mailbox Register 4

20h FIFO FIFO Register port (bidirectional)

24h MWAR Master Write Address Register

28h MWTC Master Write Transfer Count Register

2Ch MRAR Master Read Address Register

30h MRTC Master Read Transfer Count Register

34h MBEF Mailbox Empty/Full Status

38h INTCSR Interrupt Control/Status Register

3Ch MCSR Bus Master Control/Status Register

PCI BUS OPERATION REGISTERSThe PCI bus operation registers are mapped as 16 consecutive DWORD registers located at the address space(I/O or memory) specified by the Base Address Register 0. These locations are the primary method of communi-cation between the PCI and Add-On buses. Data, software-defined commands and command parameters can beeither exchanged through the mailboxes, transferred through the FIFO in blocks under program control, ortransferred using the FIFOs under Bus Master control. Table 1 lists the PCI Bus Operation Registers.

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OUTGOING MAILBOX REGISTERS (OMB)Register Names: Outgoing Mailboxes 1-4

PCI Address Offset: 00h, 04h, 08h, 0Ch

Power-up value: XXXXXXXXh

Attribute: Read/Write

Size: 32 bits

These four DWORD registers provide a method forsending command or parameter data to the Add-Onsystem. PCI bus operations to these registers maybe in any width (byte, word, or DWORD). Writing tothese registers can be a source for Add-On bus inter-rupts (if desired) by enabling their interrupt genera-tion through the use of the Add-On’s interrupt control/status register.

INCOMING MAILBOX REGISTERS (IMB)Register Names: Incoming Mailboxes 1-4

PCI Address Offset: 10h, 14h, 18h, 1Ch


Attribute: Read Only

Size: 32 bits

These four DWORD registers provide a method forreceiving user defined data from the Add-On system.PCI bus read operations to these registers may be inany width (byte, word, or DWORD). Only read opera-tions are supported. Reading from these registers canoptionally cause an Add-On bus interrupt (if desired)by enabling their interrupt generation through the useof the Add-On’s interrupt control/status register.

Mailbox 4, byte 3 only exists as device pins on theS5933 devices when used with a serial nonvolatilememory.

This location provides access to the bidirectionalFIFO. Separate registers are used when readingfrom or writing to the FIFO. Accordingly, it is not pos-sible to read what was written to this location. TheFIFO registers are implicitly involved in all bus masteroperations and, as such, should not be accessedduring active bus master transfers. When operatingupon the FIFOs with software program transfers in-volving word or byte operations, the sequenceof the FIFO should be established as described un-der FIFO Endian Conversion Management in order topreserve the internal FIFO data ordering and flagmanagement. The FIFO’s fullness may be observedby reading the master control- status registerorMCSR register.

FIFO REGISTER PORT (FIFO)

Register Name: FIFO Port

PCI Address Offset: 20h


Attribute: Read/Write

Size: 32 bits

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PCI CONTROLLED BUS MASTER WRITEADDRESS REGISTER (MWAR)Register Name: Master Write AddressPCI Address Offset: 24hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving from the Add-On bus to the PCI busduring PCI bus memory write operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MWTC, and must begin on a DWORD boundary.This DWORD boundary starting constraint is placedupon this controller’s PCI bus master transfers sothat byte lane alignment can be maintained betweenthe S5933 controller’s internal FIFO data path, theAdd-On interface, and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Write Address Register is continually up-dated during the transfer process and will always bepointing to the next unwritten location. Reading ofthis register during a transfer process (done when theS5933 controller is functioning as a target, i.e. not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master write transfers, the two leastsignificant bits presented on the PCI bus pinsAD[31:0] will always be zero. This identifies to thetarget memory that the burst address sequence willbe in a linear order rather than in an Intel 486 orPentium™ cache line fill sequence. Also, the PCI busaddress bit A1 will always be zero when this control-ler is the bus master. This signifies to the target thatthe S5933 controller is burst capable and that thetarget should not arbitrarily disconnect after the firstdata phase of this operation.

Under certain circumstances, MWAR can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Write Transfer Address (R/W)

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PCI CONTROLLED BUS MASTER WRITETRANSFER COUNT REGISTER (MWTC)Register Name: Master Write Transfer CountPCI Address Offset: 28hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master write transfer count register is used toconvey to the S5933 controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIwrite operation until the transfer count reaches zero.

Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MWTC can be ac-cessed from the Add-On bus instead of the PCI bus.See Add-On Initiated Bus Mastering.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = O's (RO)

26

00

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PCI CONTROLLED BUS MASTER READADDRESS REGISTER (MRAR)Register Name: Master Read AddressPCI Address Offset: 2ChPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

This register is used to establish the PCI address fordata moving to the Add-On bus from the PCI busduring PCI bus memory read operations. It consistsof a 30-bit counter with the low-order two bitshardwired as zeros. Transfers may be any non-zerobyte length as defined by the transfer count register,MRTC (Section 5.7) and must begin on a DWORDboundary. This DWORD boundary starting constraintis placed upon this controller’s PCI bus master trans-fers so that byte lane alignment can be maintainedbetween the S5933 controller’s internal FIFO datapath, the Add-On interface and the PCI bus.

Note: Applications which require a non-DWORDstarting boundary will need to move the first fewbytes under software program control (and withoutusing the FIFO) to establish a DWORD boundary.

After the DWORD boundary is established the S5933can begin the task of PCI bus master data transfers.

The Master Read Address Register is continually up-dated during the transfer process and will always bepointing to the next unread location. Reading of thisregister during a transfer process (done when theS5933 controller is functioning as a target—i.e., not abus master) is permitted and may be used to monitorthe progress of the transfer. During the addressphase for bus master read transfers, the two leastsignificant bits presented on the PCI bus AD[31:0]will always be zero. This identifies to the targetmemory that the burst address sequence will be in alinear order rather than in an Intel 486 or Pentium™cache line fill sequence. Also, the PCI bus addressbit A1 will always be zero when this controller is thebus master. This signifies to the target that the con-troller is burst capable and that the target should notarbitrarily disconnect after the first data phase of thisoperation.

Under certain circumstances, MRAR can be ac-cessed from the Add-On bus instead of the PCI bus.

31 0

0

1

0

2 Bit

Value

DWORD Address (RO)

Read Transfer Address (R/W)

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PCI CONTROLLED BUS MASTER READTRANSFER COUNT REGISTER (MRTC)

Register Name: Master Read Transfer CountPCI Address Offset: 30hPower-up value: 00000000hAttribute: Read/WriteSize: 32 bits

The master read transfer count register is used toconvey to the PCI controller the actual number ofbytes that are to be transferred. The value in thisregister is decremented with each bus master PCIread operation until the transfer count reaches zero.Upon reaching zero, the transfer operation ceasesand an interrupt may be optionally generated to ei-ther the PCI or Add-On bus interface. Transferswhich are not whole multiples of DWORDs in sizeresult in a partial word ending cycle. This partial wordending cycle is possible since all bus master trans-fers for this controller are required to begin on aDWORD boundary.

Under certain circumstances, MRTC can be ac-cessed from the Add-On bus instead of the PCI bus.

31 025 Bit

Value

Transfer Count in Bytes (R/W)Reserved = 0's (RO)

26

00

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MAILBOX EMPTY FULL/STATUSREGISTER (MBEF)

Register Name: Mailbox Empty/Full Status

PCI Address Offset: 34h

Power-up value: 00000000h

Attribute: Read Only

Size: 32 bits

This register provides empty/full visibility of each bytewithin the mailboxes. The empty/full status for theOutgoing mailboxes is displayed on the low-order 16bits and the empty/full status for the Incoming mail-boxes is presented on the high-order 16 bits. A valueof 1 signifies that a given mailbox has been written byone bus interface but has not yet been read by thecorresponding destination interface. A PCI bus in-coming mailbox is defined as one in which data trav-els from the Add-On bus into the PCI bus, and anoutgoing mailbox is defined as one where data trav-els out from the PCI bus to the Add-On interface.

31 015 Bit

Value

Outgoing MailboxStatus (RO)Incoming Mailbox Status (RO)

16

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Bit Description

31:16 Incoming Mailbox Status. This field indicates which incoming mailbox registers have been writtenby the Add-On interface but have not yet been read by the PCI bus. Each bit location corre-sponds to a specific byte within one of the four incoming mailboxes. A value of one for each bitsignifies that the specified mailbox byte is full, and a value of zero signifies empty. The mappingof these status bits to bytes within each mailbox is as follows:

Bit 31 = Incoming mailbox 4 byte 3Bit 30 = Incoming mailbox 4 byte 2Bit 29 = Incoming mailbox 4 byte 1Bit 28 = Incoming mailbox 4 byte 0Bit 27 = Incoming mailbox 3 byte 3Bit 26 = Incoming mailbox 3 byte 2Bit 25 = Incoming mailbox 3 byte 1Bit 24 = Incoming mailbox 3 byte 0Bit 23 = Incoming mailbox 2 byte 3Bit 22 = Incoming mailbox 2 byte 2Bit 21 = Incoming mailbox 2 byte 1Bit 20 = Incoming mailbox 2 byte 0Bit 19 = Incoming mailbox 1 byte 3Bit 18 = Incoming mailbox 1 byte 2Bit 17 = Incoming mailbox 1 byte 1Bit 16 = Incoming mailbox 1 byte 0

15:00 Outgoing Mailbox Status. This field indicates which out going mail box registers have been writtenby the PCI bus interface but have not yet been read by the Add-On bus. Each bit location correspondsto a specific byte within one of the four outgoing mailboxes. A value of one for each bit signifies thatthe specified mailbox byte is full, and a value of zero signifies empty. The mapping of these statusbits to bytes within each mailbox is as follows:

Bit 15 = Outgoing mailbox 4 byte 3Bit 14 = Outgoing mailbox 4 byte 2Bit 13 = Outgoing mailbox 4 byte 1Bit 12 = Outgoing mailbox 4 byte 0Bit 11 = Outgoing mailbox 3 byte 3Bit 10 = Outgoing mailbox 3 byte 2Bit 09 = Outgoing mailbox 3 byte 1Bit 08 = Outgoing mailbox 3 byte 0Bit 07 = Outgoing mailbox 2 byte 3Bit 06 = Outgoing mailbox 2 byte 2Bit 05 = Outgoing mailbox 2 byte 1Bit 04 = Outgoing Mailbox 2 byte 0Bit 03 = Outgoing Mailbox 1 byte 3Bit 02 = Outgoing Mailbox 1 byte 2Bit 01 = Outgoing Mailbox 1 byte 1Bit 00 = Outgoing Mailbox 1 byte 0

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INTERRUPT CONTROL/STATUSREGISTER (INTCSR)

Register Name: Interrupt Control and StatusPCI Address Offset: 38hPower-up value: 00000000hAttribute: Read/Write (R/W),

Read/Write_One_Clear (R/WC)Size: 32 bits

This register provides the method for choosing whichconditions are to produce an interrupt on the PCI businterface, a method for viewing the cause of the inter-rupt, and a method for acknowledging (removing) theinterrupt’s assertion.

Interrupt sources:

• Write Transfer Terminal Count = zero

• Read Transfer Terminal Count = zero

• One of the Outgoing mailboxes (1,2,3 or 4)becomes empty

• One of the Incoming mailboxes (1,2,3 or 4)becomes full.

• Target Abort

• Master Abort

31 015 14 12 8 4 Bit

Value16212324

FIFO and Endian Control 0

Read TransferComplete (R/WC)

Write Transfer Complete (R/WC)

Incoming Mailbox Interrupt (R/WC)

Outgoing Mailbox Interrupt (R/WC)

Interrupt Asserted (RO)

Target Abort (R/WC)

Master Abort (R/WC)

0 0 0 0

D4-D0 Outgoing Mailbox (Goes empty)

D4=Enable Interrrupt

D3-D2=Mailbox #

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D1-D0=Byte #

0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

D12-D8 Incoming Mailbox (R/W)(Becomes full)

D12=Enable Interrupt

D11-D10=Mailbox

0 0=Mailbox 10 1=Mailbox 21 0=Mailbox 31 1=Mailbox 4

D9-D8=Byte #0 0=Byte 00 1=Byte 11 0=Byte 21 1=Byte 3

Interrupt on WriteTransfer Complete

Interrupt on ReadTransfer Complete

Interrupt Source (R/W)Enable & Selection

Actual Interrupt Interrupt Selection

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0011

0 NO CONVERSION (DEFAULT)1 16 BIT ENDIAN CONV.0 32 BIT ENDIAN CONV.1 64 BIT ENDIAN CONV

FIFO ADVANCE CONTROLPCI INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

FIFO ADVANCE CONTROLADD-ON INTERFACE 0 0 BYTE 0 (DEFAULT)0 1 BYTE 11 0 BYTE 21 1 BYTE 3

OUTBOUND FIFO PCI ADD-ON DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7 (NOTE1)

INBOUND FIFO ADD-ON PCI DWORD TOGGLE0 = BYTES 0-3 (DEFAULT)1 = BYTE 4-7

NOTE 1: D24 and D25 MUST BE ALSO "1"

31 30 29 28 27 26 25 24

1

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Bit Description

31:24 FIFO and Endian Control.

23 Interrupt asserted. This read only status bit indicates that one or more of the four possible interruptconditions is present. This bit is nothing more than the ORing of the interrupt conditions describedby bits 19 through 16 of this register.

22 Reserved. Always zero.

21 Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operatesas read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a writeto this bit with the data of “zero” will not change the state of this bit.

20 Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encounteringa Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI buscycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will causethis bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.

19 Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. Thisinterrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

18 Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completionof a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. Thisinterrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates asread or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a writeto this bit with the data of “zero” will not change the state of this bit.

17 Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of thisregister are written by the Add-On interface. This bit operates as read or write one clear. A write tothis bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”will not change the state of this bit.

16 Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this registeris read by the Add-On interface. This bit operates as read or write one clear. A write to this bit withthe data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not changethe state of this bit.

15 Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the readtransfer count reaches zero. This bit is read/write.

14 Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the writetransfer count reaches zero. This bit is read/write.


12 Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identifiedby bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.

11:10 Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to bethe source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

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9:8 Incoming Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits10 and 11 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]bselects byte 2, and [11]b selects byte 3. This field is read/write.

7:5 Reserved, Always zero.

4 Enable outgoing mailbox interrupt. This bit allows a read by the Add-On of the outgoing mailboxregister identified by bits 3 through 0 to produce a PCI interface interrupt. This bit is read/write.

3:2 Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be thesource for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox 2,[10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.

1:0 Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by bits3 and 2 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1, [10]b selectsbyte 2, and [11]b selects byte 3. This field is read/write.

Bit Description

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MASTER CONTROL/STATUSREGISTER (MCSR)

Register Name: Master Control/StatusPCI Address Offset: 3ChPower-up value: 000000E6hAttribute: Read/Write, Read Only,

Write OnlySize: 32 bits

This register provides for overall control of this de-vice. It is used to enable bus mastering for both datadirections as well as providing a method to performsoftware resets.

The following PCI bus controls are available:

• Write Priority over Read

• Read Priority over Write

• Write Transfer Enable

• Write master requests on 4 or more FIFO wordsavailable (full)

• Read transfer enable

• Read master requests on 4 or more FIFOavailable (empty)

• Assert reset to Add-On

• Reset Add-On to PCI FIFO flags

• Reset PCI to Add-On FIFO flags

• Reset mailbox empty full status flags

• Write external non-volatile memory

The following PCI interface status flags are provided:

• PCI to Add-On FIFO FULL

• PCI to Add-On FIFO has four or more emptylocations

• PCI to Add-On FIFO EMPTY

• Add-On to PCI FIFO FULL

• Add-On to PCI FIFO has four or more wordsloaded

• Add-On to PCI FIFO EMPTY

• PCI to Add-On Transfer Count = Zero

• Add-On to PCI Transfer Count = Zero

31 29 27 24 23 014 12 10 8 7 6 515 Bit

Value

FIFO STATUS (RO)D5=Add-on to PCI FIFO EmptyD4=Add-on to PCI FIFO 4+ WordsD3=Add-on to PCI FIFO FullD2=PCI to Add-on FIFO EmptyD1=PCI to Add-on FIFO 4+SpacesD0=PCI to Add-on FIFO Full

D7=Add-on to PCI Transfer Countequals zero (R0)

D6=PCI to Add-on Transfer Countequals zero (R0)

160

Write Transfer Control (R/W)(PCI memory writes)

D10=Write Transfer EnableD9=FIFO Management SchemeD8=Write vs Read Priority

Reset Controls (R/WC)D27=Mailbox Flags ResetD26=Add-on to PCI FIFO Status Flags ResetD25=PCI to Add-on FIFO Status Flags ResetD24=Add-On Reset nv operation address/data

Memory Read MultipleEnable = 1Disable = 0

Read Transfer Control (R/W) (PCI memory reads)

D14=Read Transfer EnableD13=FIFO Management SchemeD12=Read vs. Write Priority

nvRAM Access Ctrl

0 0

Control Status

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Bit Description

31:29 nvRAM Access Control. This field provides a method for access to the optional external non-volatilememory. Write operations are achieved by a sequence of byte operations involving these bits and the8-bit field of bits 23 through 16. The sequence requires that the low-order address, high order address,and then a data byte are loaded in order. Bit 31 of this field acts as a combined enable and ready forthe access to the external memory. D31 must be written to a 1 before an access can begin, andsubsequent accesses must wait for bit D31 to become zero (ready).

D31 D30 D29 W/R

0 X X W Inactive

1 0 0 W Load low address byte

1 0 1 W Load high address byte

1 1 0 W Begin write

1 1 1 W Begin read

0 X X R Ready

1 X X R Busy

Cautionary note: The nonvolatile memory interface is also available for access by the Add-Oninterface. Accesses by both the Add-On and PCI bus to the nv memory are not directly supportedby the S5933 device. Software must be designed to prevent the simultaneous access of nvmemory to prevent data corruption within the memory and provide for accurate data retrieval.

28 FIFO loop back mode.

27 Mailbox Flag Reset. Writing a one to this bit causes all mailbox status flags to become reset (EMPTY).It is not necessary to write this bit as zero because it is used internally to produce a reset pulse. Sincereading of this bit will always produce zeros, this bit is write only.

26 Add-On to PCI FIFO Status Reset. Writing a one to this bit causes the Add-On to PCI (Bus mastermemory writes) FIFO empty flag to set indicating empty and the FIFO FULL flag to reset and the FIFOFour Plus word flag to reset. It is not necessary to write this bit as zero because it is used internallyto produce a reset pulse. Since reading of this bit will always produce zeros, this bit is write only.

25 PCI to Add-On FIFO Status Reset. Writing a one to this bit causes the PCI to Add-On (Busmaster memory reads) FIFO empty flag to set indicating empty and the FIFO FULL flag to resetand the FIFO Four Plus words available flag to set. It is not necessary to write this bit as zerobecause it is used internally to produce a reset pulse. Since reading of this bit will always producezeros, this bit is write only.

24 Add-On pin reset. Writing a one to this bit causes the reset output pin to become active. Writing azero to this pin is necessary to remove the assertion of reset. This register bit is read/write.

23:16 Non-volatile memory address/data port. This 8-bit field is used in conjunction with bit 31, 30 and29 of this register to access the external non-volatile memory. The contents written are either lowaddress, high address, or data as defined by bits 30 and 29. This register will contain the externalnon-volatile memory data when the proper read sequence for bits 31 through 29 is performed.

PCI 150

73

Bit Description

15 Enable memory read multiple during S5933 bus mastering mode.

14 Read Transfer Enable. This bit must be set to a one for S5933 PCI bus master read transfers totake place. Writing a zero to this location will suspend an active transfer. An active transfer is onein which the transfer count is not zero.

13 Read FIFO management scheme. When set to a 1, this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more vacant FIFO locations to fill. Once the controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevacant FIFO word.

12 Read versus Write priority. This bit controls the priority of read transfers over write transfers.When set to a 1 with bit D8 as zero this indicates that read transfers always have priority overwrite transfers; when set to a one with D8 as one, this indicates that transfer priorities willalternate equally between read and writes.


10 Write Transfer Enable. This bit must be set to a one for PCI bus master write transfers to takeplace. Writing a zero to this location will suspend an active transfer. An active transfer is one inwhich the transfer count is not zero.

9 Write FIFO management scheme. When set to a one this bit causes the controller to refrain fromrequesting the PCI bus unless it has four or more FIFO locations filled. Once the S5933 controlleris granted the PCI bus or is in possession of the bus due to the write channel, this constraint isnot meaningful. When this bit is zero the controller will request the PCI bus if it has at least onevalid FIFO word.

8 Write versus Read priority. This bit controls the priority of write transfers over read transfers.When set to a one with bit D12 as zero this indicates that write transfers always have priority overread transfers; when set to a one with D12 as one, this indicates that transfer priorities willalternate equally between writes and reads.

7 Add-On to PCI Transfer Count Equal Zero (RO). This bit is a one to signify that the write transfercount is all zeros.

6 PCI to Add-On Transfer Count Equals Zero (RO). This bit is a one to signify that the read transfercount is all zeros.

5 Add-On to PCI FIFO Empty. This bit is a one when the Add-On to PCI bus FIFO is completelyempty.

4 Add-On to PCI 4+ words. This bit is a one when there are four or more FIFO words valid withinthe Add-On to PCI bus FIFO.

3 Add-On to PCI FIFO Full. This bit is a one when the Add-On to PCI bus FIFO is completely full.

2 PCI to Add-On FIFO Empty. This bit is a one when the PCI bus to Add-On FIFO is completelyempty.

1 PCI to Add-On FIFO 4+ spaces. This bit signifies that there are at least four empty words withinthe PCI to Add-On FIFO.

0 PCI to Add-On FIFO Full. This bit is a one when the PCI bus to Add-On FIFO is completely full.

ADC: 12/14/16 BITS - 200.000 SPS PCI 150 · 2018. 10. 12. · IMB1 MBEF INTCSR MCSR CONFIGURATION...

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Transcript of ADC: 12/14/16 BITS - 200.000 SPS PCI 150 · 2018. 10. 12. · IMB1 MBEF INTCSR MCSR CONFIGURATION...