TRAPPISTETracking Particles for Physics Instrumentation in

SOI Technology

Prof. Eduardo Cortina, Lawrence Soung Yee

Institut de recherche en mathématique et physique

Center for Cosmology, Particle Physics and Phenomenology

10 November, 2011 SCK-CEN Meeting 1

Hybrid vs. Monolithic Detectors

10 November, 2011 SCK-CEN Meeting 2

- Integration problems- Production yield- Fragility

- Sensor and electronics isolation

- “Non standard” process

Monolithic Detector in SOI Technology

Active layer: ~50nmContains readout electronics

Buried Oxide (BOX): ~200nmInsulates circuit from detector

Handle wafer: ~300µmContains the detector.The backside metal is biased to deplete the detector.

p+n+

++

+

---

10 November, 2011 SCK-CEN Meeting 3

TRAPPISTE-12μm Fully Depleted SOI CMOS at WINFAB at UCL

Shift register to control readout column by column.

3cm

8x8 matrix of 300μmx300μm pixel cells with 3 transistor readout.

10 November, 2011 SCK-CEN Meeting 4

TRAPPISTE-2

2.5mm

2.5m

m

Transistor test area7 column source tied transistors.

CSA test areaAmplifiers chain with standard and low voltage threshold transistor.

3T MatrixStandard 3-transistor readout chainEach pixel 150µm x 150µm

CSA MatrixCharge sensitive amplifier readout chainEach pixel 150µm x 150µm

0.2µm fully depleted (FD-SOI) CMOS by OKI Semiconductor, Japan

10 November, 2011 SCK-CEN Meeting 5

Pixel Matrix

A matrix of pixels with three transistor readout.- Readout controlled by a shift register to activate on column at a time- Different shaped implants to improve breakdown voltage

10 November, 2011 SCK-CEN Meeting 6

Readout Chain

Rf

Cf

Charge SensitiveAmplifier

VthCdif

Rdif

Rint

Cint

Shaping Amplifier DigitizerDetector

10 November, 2011 SCK-CEN Meeting 7

Amplifier Measurements

Injected charge (1MIP)

Output of shaper

Output of CSA

Parameters Specification

Power supply VDD +1.8

Detector Capacitance Cd 0.25pF

Detector Signal 1 MIP ( 23.000e-)

Feedback resistance RF >100MΩ

Feedback capacitance CF 37.57fF

TRAPPISTE-2 Data

10 November, 2011 SCK-CEN Meeting 8

CSA DC Sweep

DC Sweep Characterizations- Simulations match measurements- Shift of transfer curve with bias ring voltage

10 November, 2011 SCK-CEN Meeting 9

Test System

FPGA board to program test routines.

Main board:- Voltage and current sources- DACs to set appropriate biases- ADC to read output voltages

Daughter board to accommodate test devices and package types.

10 November, 2011 SCK-CEN Meeting 10

Schedule

10 November, 2011 SCK-CEN Meeting 11

Start of TRAPPISTE project 2008

TRAPPISTE-1 2009

TRAPPISTE-2 2011

TRAPPISTE-3Laser and beam testsL. Soung Yee PhD

2012

TRAPPISTE-4P. Alvarez PhD (UAB)

2013

TRAPPISTE-5 (engineering model) 2015

Manpower required: 1 Post-doc + 1 PhD

Backup Slides

10 November, 2011 SCK-CEN Meeting 12

Measurement of Transistor Characteristics

Influence of back bias on transfer curves and transistor parameters.

10 November, 2011 SCK-CEN Meeting 13

Discriminator Measurements

Discriminator measurements- Output for various threshold voltages- Influence of bias on detector ring

10 November, 2011 SCK-CEN Meeting 14