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Global Energy Interconnection

Full-length article

Systematic design method for PI controller with Virtual Resistor-based Active Damping of LCL filter

Marwa Ben Saïd-Romdhane1, Mohmed Wissem Naouar1, Ilhem Slama-Belkhodja1

1. Université de Tunis El Manar, Ecole Nationale d’Ingénieurs de Tunis, LR 11 ES 15, Laboratoire des Systèmes Electriques, BP 37-1002, Tunis le Belvédère, Tunisie

Abstract: The Virtual Resistor based Active Damping (VR-AD) is widely employed in converters connected to the grid via LCL filters in order to mitigate the inherent resonance of the filters. Nevertheless, in digitally controlled systems, the PWM and the calculating delays modify the system characteristics in terms of frequency and phase, thus destabilizing the system and degrading the VR-AD performances, mainly in low switching frequencies. Moreover, the stability of the system is greatly affected under weak grid operation characterized by large grid impedance variation. This paper solves these problems by proposing a systematic, robust and optimized design procedure of voltage oriented PI control (VOC) with VR-AD. The considered design procedure ensures robust control (sufficient stability margins) and high quality of grid current (reduced steady-state error and minimized THD value) despite the negative impact of digital time delay, grid impedance variation and filter parameters change. Simulation and experimental results are presented to show robustness and efficiency of the suggested design procedure.

Keywords: Digital controllers, LCL filter, Time delay, Grid-connected converters, Virtual Resistor, Real Resistor, VOC, Grid impedance variation, Controllers design.

1 Introduction

Grid-connected converters (GcCs) constitute an indispensable intermediate between the power grid and distributed generation systems. To mitigate the switching harmonics produced by these converters, LCL filters are usually used. This is due to the fact that this type of filters offers high attenuation ability with reduced size and cost [1-3]. However, the LCL filter resonance may destabilize the closed loop control of the system [4]. To overcome this issue, several passive and active damping methods are suggested to enhance the stability of the

Received: 3 June 2018/ Accepted: 27 June 2018/ Published: 25 August 2018

Marwa Ben Saïd-Romdhane marwa.bensaidromdhane@enit.utm.tn

Mohamed Wissem Naouar mohamed.wissem@enit.utm.tn

Ilhem Slama-Belkhodja ilhem.slamabelkhodja@enit.utm.tn

system. Active damping methods (AD) are more adopted than passive damping ones (PD), since they ensure better damping without additional power loss and heat dissipation apparatus [5-7].

The Virtual Resistor based Active Damping (VR-AD) combines the advantages of both PD and AD methods. In fact, it gives high damping performances as the real resistor-based passive damping RR-PD, while avoiding supplementary power loss and encumbrance [8,9]. In addition, compared to other AD methods, the VR-AD is characterized by its robustness, simple implementation and high efficiency [10,11]. Nevertheless, the VR-AD features may be affected in digitally controlled systems due to the time associated delay [12,13]. In fact this digital time delay can change the impedance characteristics of the VR-AD and reduces the system phase margin, resulting in poor robustness, especially in low switching frequencies [14,15]. This time delay is indispensible in digitally controlled systems since it incorporates the computation and the PWM delays.

Another key factor that affects the system stability is the large grid impedance variation Lg [16-18]. In fact, in weak

Vol. 1 No. 3 Aug. 2018

DOI: 10.14171/j.2096-5117.gei.2018.03.003

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Global Energy Interconnection Vol. 1 No. 3 Aug. 2018

grids, the Lg values can vary significantly due to low power capacity transformers, parallel connections of GcCs and long distribution wires [18,19]. The goal of this paper is to suggest a systematic, robust and optimized design procedure for the VOC with VR-AD for LCL-GcC. Compared to previous associated works [19-26], the suggested design procedure takes into account the following restrictions that may threaten the stability of the system: 1) time delay of digital controllers, 2) filter parameters changes and 3) large grid inductance variations. Although under the above mentioned restrictions, the suggested design procedure ensures the following performances: 1) sufficient phase margins and gain margins, 2) the minimized grid current THD value and 3) the minimized steady-state error.

This paper is organized as follows. Firstly, in section II, the VOC with VR-AD for LCL-GcC is presented. After that, in section III, the controllers design procedure of the VOC with VR-AD is detailed and discussed. After that, in section IV, simulation results obtained via Matlab-Simulink are presented. Finally, section V is devoted to experimental tests. The obtained experimental results prove robustness and effectiveness of the suggested design procedure.

2 VOC with VR-AD for LCL-GcC

The LCL-GcC power circuit and the VOC with VR-AD are presented by Fig.1 (a) and Fig.1 (b), respectively. As depicted in Fig.1 (b), the control strategy is composed of

several modules which are:- DC-link voltage control module: This module controls

the DC-link voltage Vdc via a PI controller. It generates the reference current i2d

* from the difference between reference

DC-link voltage Vdc* and the measured one Vdc.

- Grid synchronization module: The aim of this module is to compute the position of the grid voltage vector θdq. This position is used in the abc-to-dq and dq-to-abc coordinate transformations.

- Grid currents regulation module: This module is based on a PI controller and in the dq reference frame. It controls the grid-side currents. The d-axis grid current reference i2d

* is

determined by the DC-link voltage control module. The q-axis grid current i2q

* is imposed equal to zero to ensure a

unit power factor operation.-VR-AD module: This module is based on a virtual

resistor used to actively reduce the resonance of the LCL filter. This virtual resistor is equivalent to a real damping resistor placed in series with the filter capacitor. Compared to the RR-PD, the VR-AD ensures better current harmonic attenuation without extra power loss and encumbrance.

- PWM module: The Pulse Width Modulation module determines the power converter switching states during the kth

sampling period.Fig.2 shows the timing diagram of the implemented

VOC with VR-AD that presents the PWM references sampling and update instants and the execution time of the different aforementioned modules. As shown in this figure,

i2a

C

ic ScSa

ScSa

Sb

Sb

Li L2

LCL FilterLg

i2b

i2c

iia iib iic

GridPower converter is idc

Vga

Vgb

Vgc

Via

Vib

Vic

Renewable energy source

or load Vdc

Vcc

Vca

Vcb

Cf

Vdc i2(a ,b,c) Vg(a ,b,c)S(a ,b,c)

Digital controller

+ -

Vdc*

Vdc

PI i2d

*

DC-link voltagecontrol loop

(b)

+ PI

PI

+ +

+

dq-to-abc

+

θdq

Vgd-ωg L2gi2q

Vgq+ωg L2gi2d

Vi(a ,b,c)*

S(a ,b,c) PWM

VR-AD

Kr

+

icd

-

Vid*

Viq*

icq

(a)

Grid synchronization

Grid synchronization

Vg(a,b,c) θdq

i2q

-

abc-to-dq θdq

i2q* + -

i2d

i2(a,b,c)

abc-to-dq θdq

ic(a,b,c)

Kr - +

L2g

LTg

ica icb icc

Fig. 1 (a) LCL-GcC (b) VOC with VR-AD

321

Marwa Ben Saïd-Romdhane et al. Systematic design method for PI controller with Virtual Resistor-based Active Damping of LCL filter

the input variables Vdc, Vg(a,b,c), i2(a,b,c) and ic(a,b,c) are sampled at higher carrier vertexes, while the converter voltage vector is updated. Consequently, the time delay is equal to the sampling period Ts. In Fig.2, tPI_Vdc, tθdq, tPI_i2, tVR-AD

and tPWM are the execution time of the respective modules: DC-link voltage control module, grid synchronization module, grid currents regulation module, VR-AD module and PWM module. Table 1 shows the system and LCL filter parameters. Also, tAD and Tex are, respectively, the A/D conversion time and the execution time.

are: 1) LCL filter parameters uncertainties, overestimated to ±20%; 2) time delay related to digital controllers and 3) large grid impedance variation, overestimated to 13 mH. While the desired performances are: 1) reduced steady-state error (EA < 5%); 2) sufficient gain margin (Gm < 9 dB); 3) sufficient phase margin (45°< Pm <65°) and 4) reduced grid current THD (THDi2 < 5%). The next step consists in computing the integral gain Ki according to the requirement on the steady state error. After that, the virtual resistor Kr is computed considering a well damped RR-PD. Afterward, in the fourth step, the proportional gain Kp is deduced from the region where the desired restrictions on Gm and Pm

are ensured. Then, in the fifth step, the designer should verify that the obtained controllers parameters ensure a grid current THD less than 5% according to the IEEE 519-1992 standard. If this is not the case, the designer should increase the value of the virtual resistor Kr. In the sixth step, the designer should verify that, for the obtained controllers parameters, the desired performances are ensured even for LCL filter parameters uncertainties. If this is not the case, the designer should increase the value of the Kp, while ensuring the desired restrictions on Gm and Pm. Finally, in the last step, are presented the final controllers parameters that ensure the desired performances even under the constraints defined in the first step. The different steps of the controllers design method are presented and detailed in the following paragraphs.

Constraints: 1) Lg [0, 13mH] 2) Time delay = Ts 3) Filter parameters change (overestimated to ±20%)

Performances: 1) EA < 5% 2) Gm > 9dB 3) 45° <Pm< 65° 4) Grid current THD < 5%

No

Yes

THDi2<5%

Determination of Kp Requirement on Pm, Gm and transient response

Determination of Kr RR-PD

Determination on Ki Requirement on EA Step 2

Step 3

Step 4

Final values of controllers parameters Kr, Kp and Ki Step 7

No

Yes

Robustness against filter parameters

variations

↑ Kr

Step 5

Step 6

Step 1

↑ Kp

∈

t(s)

kTs Update Vi

*(a,b,c) [k-1]

Sample Vg(a,b,c)[k], Vdc[k], i2(a,b,c)[k] and ic(a,b,c)[k]

(k+1)Ts Update Vi

*(a,b,c) [k]

Sample Vg(a,b,c)[k+1], Vdc[k+1], i2(a,b,c)[k+1] and ic(a,b,c)[k+1]

Ts Tex

Carrier

tAD tPI_Vdc tθdq tPI_i2 tVR-AD tPWM t(s)

Tex

Fig. 2 PWM references sampling and update instants

Table 1 Parameters of the system

Parameter Description Value

System

UgLine-to-line RMS grid

voltage400 V

P Rated active power 4 kW

fsωSwitching frequency of the

converter10 kHz

foRated frequency of grid

voltage50 Hz

Vdc DC-link voltage 600 V

LCL filter

C Capacitor filter 4 µF

Li Converter side inductance 5 mH

L2 Grid side inductance 2 mH

Grid inductance

LgInductive part of the grid

impedance

Lgmin=0 mH and

Lgmax=13 mH

3 Control parameters tuning

Fig.3 presents the diagram that gives the different steps of the proposed controllers parameters tuning method. As shown in this figure, in the first step are defined the constraints and the desired performances. These constraints

Fig. 3 Controllers parameters design algorithm

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Global Energy Interconnection Vol. 1 No. 3 Aug. 2018

3.1 Tuning of Ki

Since the delay caused by the PWM process is negligible with regard to the dynamic of the coupling terms ±ωgL2

gi2dq and since the value of these terms can be assumed constant between two consecutive periods, Fig.1(b) can be simplified as in Fig.4(a) [8,26]. This figure gives the simplified discrete z-domain dq-axis block diagram of the VOC with VR-AD. In this figure, KPWM is the PWM converter gain and e-sTs

is the computation delay. Gr and Hr are the transfer functions from i2dq to Vidq and from icdq to Vidq, respectively. Gr and Hr are expressed by equations (1) and (2), respectively.

(1)

(2)

According to (1), (2) and Fig.4 (a), the transfer function GADr is expressed by (3).

(3)

According to Fig.4 (a) and (3), the system open loop transfer function is given by (4).

(4)

The control strategy employed for controlling the grid-side currents is based on a VOC designed in the dq reference frame. For that case, the controlled i2dq currents are continuous signals during steady state operation. Thus,

( )22

22

resgT

res

idq

dqr ssLV

iG

ωω+

==

( )22resiidq

cdqr sL

sVi

Hω+

==

sLsCeLKKCsLLeK

eHKKeGK

Vi

G

gT

sTgrPWM

gi

sTPWM

sTrrPWM

sTrPWM

nrdq

dqADr

S

s

s

s

++=

+==

−

−

−

−

22

32

2

1

sLsCeLKKCsLLeGK

ii

T gT

sTgrPWM

gi

sTPIPWM

dq

dq

S

s

++=

∆= −

−

22

322

2

during steady state operation, the use of PI controllers will lead to an amplitude error equal to zero. As regards the phase error, we firstly notice that the grid voltage phase θdq

is determined with good accuracy using well-known grid synchronization techniques. As a result, the phase error is zero during steady state operation thanks to the use of the abc-to-dq and dq-to-abc coordinate transformations. However, during transient states caused, for example, by random swings of the active (or reactive) power drawn by the LCL-GcCs, the i2dq currents are time-varying, which will result in amplitude and phase errors. However, given that the proposed design method ensures the achievement of a high bandwidth control, the amplitude and phase error will be very low during the transient state operation. Since the grid voltage phase is determined with good accuracy, only the amplitude error EA will be considered in this paper and it is expressed by equation (6) [28]. In equation (6), |Tfo| denotes the system open loop transfer function gain at the fundamental frequency fo. Since the simplified transfer function of the PI controller (5) for fundamental frequency fo is given by (7), and based on (4), neglecting the influence of the filter capacitor at fo, |Tfo| is given by (8).

(5)

(6)

(7)

(8)

According to (8), EA depends on the integral gain Ki. Consequently, the choice of Ki depends on the restrictions of steady-state error. For an EA less than 5%, |Tfo| should be larger than 26dB. Therefore, in order to ensure EA less than

( )s

KKsG ipPI +=

foTAE 20

1

10−

≈

o

ioPI fj

KfjGπ

π2

)2( ≈

( )

=≈=

AogT

PWMiofo EL

KKfjTT 1log202 102ωπ

Fig. 4 (a) Block diagram of the system with VR-AD in the dq reference frame (b) Simplified equivalent block diagram

i2dq* +

- i2dq

+-

icdq Vcdq

-+

Vidq iidq

+

- +

Vgdq

1sC

1LisGPI

- Kr

icdq i2dq

Converter and LCL filter Current controller

Δi2dq

Vnrdq

Ts

ZOH

Vmrdq

e-sTs KPWM1

L2gs

Ts

Ts

(a)

+Vgdq

i2dq* +

-i2dq

+-

Vidq

GPI

Kr

GADr

Δi2dq

Vnrdq

Ts

ZOH

Vmrdq

e-sTs KPWM

Ts

Ts

Gr

Hr

icdq

(b)

+Vgdq

323

Marwa Ben Saïd-Romdhane et al. Systematic design method for PI controller with Virtual Resistor-based Active Damping of LCL filter

5% even for large grid impedance variation, Ki must satisfy equation (9). A value of 40000 is selected for Ki.

(9)

3.2 Tuning of Kr

The virtual resistor Kr is selected according to a well damped RR-PD. Thus, the choice of the real resistor value is an important step. This choice should be a compromise between low power loss and sufficient stability margins. The real damping resistor is computed based on the following equation. [29]

(10)

The real resistor Rd produces power loss Pd expressed by (11), where iin and i2n denote the nth

harmonic order of the inverter and grid current, respectively. The obtained power loss associated to Rd is equal to 4.5W which represents 0.1% of the rated active power P.

(11)

Fig.5 reports the root locus of the T transfer function when Rd varies from 0 to 30 Ω. According to this figure, the system stability is improved as Rd rises. However, the rise of Rd will produce higher Pd. According to Fig.5, for Rd=6Ω (the computed value), the obtained gain margin Gm is equal to 47° and the obtained phase margins Pm is equal to 9.12 dB, while the obtained power loss Pd represents only 0.1% of P. Consequently, the obtained damping resistor (Rd=6Ω) is a good compromise between power loss and stability. Fig.6 (a) presents the single phase representation of an un-damped LCL filter in high frequencies. According to the power circuit given by Fig.6 (a), F1 from Vco to Vi is expressed by (12.a), whereas, that from ic to Vco is expressed by (12.b). Based on (12.a) and (12.b), the block diagram of the un-damped high frequency LCL filter can be deduced as is Fig.6 (c). Based on this diagram and Fig.4, the VR-AD can be simplified as in Fig.6 (d). According to the obtained modified system given, the transfer function H from Vco to Vi is expressed by (12.c). On the other hand, based on Fig.6 (b), which presents the single phase representation of an LCL filter damped with a real resistor Rd in high frequencies, the transfer function G from VcR to Vi is expressed by (12.d). To ensure that the system with VR-AD has the same poles as the system with RR-PD, the denominators of F and G should be equal. Consequently, the virtual resistor Kr value is selected based on (12.e), and Kr is equal to 18 since the correspondent Rd is equal to 6Ω.

[ ]33359

13,026 2 ∈i

g

PWM

ogT

i KmHL

KLK ω

Ω=×

== 623

13

1CfC

Rresres

d πω

( ) WPiiRP dR

nnindd

d 5.43 622 = →−= Ω=∑

(a) (b)

(c) (12) (d)

(e)

3.3 Tuning of Kp

The choice of Kp is based on the requirements on the gain and phase margins Gm and Pm. Since the phase plot will cross over -180° only once at fres, Gm is given by the following equation:

(13) Substituting (5) into (4) and according to (13), Gm is

given by the following equation:

-1.5

-1

-0.5

0

0.5

1

1.5 × 104 Pole-Zero Map

-4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5× 104Real Axis

Imag

inar

y A

xis

Rd

Rd

Rd

Rd

Rd =6Ω

Lg =0mH

(a)

Fig. 5 Closed-loop system Root locus for Rd includes in [0 30Ω]

(c)

Vi VcoF1(s)

F2(s)ic (a)

Liii

Vi Vco C

ic

L2 i2

Vg=0

+-

F1(s)

F2(s)ic Kr

Vi

(d)

Vco

(b)

Liii

Vi VcR C

ic

L2 i2

Vg=0 Rd

Fig. 6 (a) High frequency single phase circuit of an un-damped LCL filter

(b) High frequency single phase circuit of an LCL filter damped with a real resistor Rd

(c) LCL filter block diagram (d) Modified control structure

( )( )( )

2

2

22

2

2

22r2

2

2

2

22

2

21

11

LLLRK

LLRsCCsLLRsCL

VVG

LLsLCKCsLLL

VVH

sCViF

LLCsLLL

VVF

idr

idi

df

i

cR

iii

co

co

c

iii

co

+=⇒

+++

+==

+++==

==

++==

( )resm fjTG π2log20 10−=

324

Global Energy Interconnection Vol. 1 No. 3 Aug. 2018

(14)

Since Gm should be greater than 9dB although large grid impedance changes and according to (14), Kp must verify condition (15). For Ki equals to 40000, Kr equals to 18 and Lg

varies up to 13mH, Kp must be less than 4.8 as shown in (15).

(15)

The selection of Kp can be refined by the requirement of Pm which is expressed as in (16). Based on (16), (4) and (5), the expression of Pm is given by (17).

(16)

(17)

where fc is the crossover frequency. Since the influence of the filter capacitor can be ignored for frequencies up to fc

and according to (4), the gain of T(s) at fc is expressed by (18). In addition, the PI controller can be simplified to Kp at fc as given in (19). Since |T(s)| is unity at fc and substituting (19) into (18), fc is given by equation (20).

(18)

(19)

(20)

Finally, the Pm of the system is expressed as follows

(21)

( )

( )( )( )( )ressPWMr

gressPWMr

ggTres

gi

res

resPiPWMm

TKKCLTKKCLLCLLA

AKKK

G

ω

ωω

ωω

cos

sin

log20

2

2

22

22

2

22

10

+

−−=

+−=

([]( )) ( )( )

[ ] 8.4

cossin

10

13,040000

118

222

2

22

2410

9

→

−+

− −=

∈=

==

−

pmHL

KKK

iressPWMrg

ress

PWMrg

resg

res

resp

K

KTKKCLT

KKCLCLiLB

BK

g

i

PWMr

ωω

ωω

ωgL2

( )( )cm fjTP π2arg180 +=

( ) ( )( ) ( )( ) ( )

( )( ) g

TcsresPWMrfg

resfg

i

csresPWMrfg

cspcscp

csicscp

m

LfTKKCLCLLfTKKCL

D

fTKfTKfTKfTK

C

DCP

−−

−=

+

−=

−+= −−

πωωπω

ππωππω

2sin2cos

2cos2sin2sin2cos

tantan180

222

2

11

( ) ( )cPIc

gT

PWMccf jG

LKjT ωω

ω ≈

( ) pcPI KjG ≈ω

gT

pPWMc L

KKf

π2≈

Fig.7 shows the phase margin Pm (equation (21)) with regard to Lg variations for Kp included in [0, 4.8] (value that ensures a gain margin greater than 9 dB (condition given by (15)). According to Fig.7, when Lg rises, Pm is degraded for several values of Kp. The variation interval that ensures simultaneously a 45°<Pm<65° and a Gm>9 dB is [1.8, 3.2]. A value of 2.5 is selected for Kp.

3.4 Requirement on the grid current THD

Fig.8 shows the grid current THDi2 for different values of Lg and Kr. It can be noted, according to this figure, that when Kr and Lg rise, the grid current decreases. In this step, the designer verifies that for the obtained controllers parameters, the obtained THDi2 is well below 5%. If this is not the case, the value of the virtual resistor Kr should be increased. As shown in Fig.8, for the obtained controllers parameters, the THDi2 is equal to 1.2% and 0.7% for Lg equals to 0mH and 13mH, respectively.

1020

30 0,0030,006

0,009

THD i2(% )

Lg(mH )

5

3Kr

6

13 2

10

30 20

40

9

0

THDi2 =1.2% Kr=18 Lgmin=0 mH

THD i2 =0.7 % Kr=18 Lgmax=13 mH

0

Fig. 8 Grid current THD according virtual resistor and grid inductor

( ) ( )

gTg

T

PWMpsresPWMrf

gresf

gi

gT

PWMpsresPWMrf

g

gT

PWMpsig

T

PWMpscp

gT

PWMpsig

T

PWMpscp

m

LLKKT

KKCLCLL

LKKT

KKCLF

LKKT

KLKKT

K

LKKT

KLKKT

KE

FEP

−

−

−

=

−

−

=

−+= −−

sin

cos

cossin

sincos

tantan180

22

2

2

11

ωω

ω

ω

ω

( ) ( )

gTg

T

PWMpsresPWMrf

gresf

gi

gT

PWMpsresPWMrf

g

gT

PWMpsig

T

PWMpscp

gT

PWMpsig

T

PWMpscp

m

LLKKT

KKCLCLL

LKKT

KKCLF

LKKT

KLKKT

K

LKKT

KLKKT

KE

FEP

−

−

−

=

−

−

=

−+= −−

sin

cos

cossin

sincos

tantan180

22

2

2

11

ωω

ω

ω

ω

45

Lgmin=0

65

Lg(mH)

Lgmax=13

Constrained by 45°< Pm<65°

Kp↑

Pm(°)

Kp=4.8Kp=4 Kp=3.2Kp=2.6Kp=1.8Kp=1 Kp=0.2

Fig. 7 Phase margin Pm according to grid impedance

325

Marwa Ben Saïd-Romdhane et al. Systematic design method for PI controller with Virtual Resistor-based Active Damping of LCL filter

3.5 Robustness against filter parameters change

In this step, the designer verifies that the selected control parameters values ensure robust stability of the system despite filter parameters change. In order to verify this condition, the Bode diagrams of T(s) are plotted taking into account the Lg changes and the filter parameters uncertainties. In Fig.9, C varies from 1.6 μF to 2.4 μF (2 μF±20%), in Fig.10, Li varies from 4 mH to

6 mH (5 mH±20%) and in Fig.11, L2 varies from 1.6 mH to 2.4 mH (2 mH±20%). In these figures, Lg is set to 13 mH. According to these figures, Gm is greater than 15.8 dB and Pm is greater than 37.8° for all the cited cases. In addition, |Tfo| is greater than 31.3 dB, which corresponds to an EA

equal to 0.85.

4 Simulation results

Table 2 presents the controllers parameters obtained based on the suggested design procedure as well as the obtained performances for Lg=0 and Lg=13 mH. As depicted on this table, the desired requirements on EA, fc, Pm and Gm are achieved even for huge changes on Lg. During simulation tests under Matlab-Simulink, the fsω

is equal to 10 kHz. Fig.12 presents the response of the dc-link voltage Vdc. As shown in this figure, Vdc is well regulated during steady state operation since it reaches its reference which is equal to 150 V. Fig.13 presents the waveforms of the grid current and voltage (i2a and Vga) during steady state operation. This figure shows that a unit power factor operation is ensured. Fig.14 presents the waveform of the grid current i2a for Lg equal to zero. The obtained simulated grid current i2a and its reference value i2a

* are equal to 1.218A and 1.22A, respectively. Thus,

the obtained EA is equal to 0.12%. Moreover, it should be noticed that, the obtained grid current THD is equal to only 1.2%. The obtained EA and THD value show the high quality of the grid current. Supplementary inductors of 13 mH are placed in series with L2 to prove the robustness of the VR-AD. As depicted in Fig.14, the system stability is ensured even for weak grid conditions. In addition, for Lg equal to 13 mH, the THD value of the simulated grid current is equal to 0.7%. It can be noted according to the obtained simulation results that the implemented VR-AD is robust and thus the proposed controllers design procedure is efficient.

Table 2 Controller Parameters

Parameter Value

Controller

Kp 2.5

Ki 40000

Kr 18

Performances

Lg Lg=0 mH Lg=13 mH Constraints

Pm 64.1° 47.3° 45°<Pm<65°

Gm 23.5 dB 19.4 dB Gm>9 dB

|Tfo| 57.89 dB 26.5 dB |Tfo|>26 dB

EA 0.12% 4.7% EA<5%

THD(i2) 1.2% 0.7% THD(i2)<5%

Frequency (Hz)

|T f0(min)| =32.6 dB G m(min) =19.6 dB

Pm(min)=38.4°

10-1 100 101 102 103

Bode Diagram

- 50

0

50

100

150

-360

-270

-180

- 90

L 2=1.6 mH

L 2=2.4 mHL 2=2 mH

L 2=1.6 mH

L 2=2.4 mH L 2=2 mH

Mag

nitu

de(d

B)Ph

ase(

deg)

Frequency (Hz)

|T f0(min)| =36 dB G m(min) =15.8 dB

Pm (min)=37.8°

10-1 100 101 102 103

Bode Diagram

-50

0

50

100

150

-360

-270

-180

L i=4 mH

L i=6 mHL i=5 mH

L i=4 mH

L i=6 mHL i=5 mH

Mag

nitu

de(d

B)Ph

ase(

deg)

Fig. 10 Bode diagrams of the open loop system for Lg equal to 13 mH, Li varies from 4 mH to 6 mH (5 mH±20%)

Frequency (Hz)

|Tf0(min)| =31.3 dB Gm(min) =17.4 dB

Pm(min)=39.2°

10-1 100 101 102 103

C =1.6 µF

C =2.4 µFC =2 µF

C =1.6 µF

C =2.4 µFC =2 µF

Bode Diagram

-50

0

50

100

150

-360

-270

-180

-90

Mag

nitu

de(d

B)Ph

ase(

deg)

Fig. 9 Bode diagrams of the open loop system for Lg equal to 13 mH, C varies from 1.6 μF to 2.4 μF (2 μF±20%)

Fig. 11 Bode diagrams of the open loop system for Lg equal to 13 mH, L2 varies from 1.6 mH to 2.4 mH (2 mH±20%)

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Global Energy Interconnection Vol. 1 No. 3 Aug. 2018

Vdc*

InitialVdc

Vdc

Load connection

0 0.1 0.2 0.3 0. 4

L g=0 mH

t (s)

Fig. 12 Vdc response for Lg=0 mH

i 2a

(b)

0.4

0A

Lg=0mH

t (s)

fsω=10 kHz

0.32 0.34 0.36 0.38

I2max

-I2max

i 2a

L g=0 mH

THD i2 =1.2%

0.30

Fig. 13 i2a and Vg waveforms for Lg=0 mH

THD(i2a)=1%

0A

- I2max (d)

Lg=0mH

t (s)

i2a

0.3 0.4 0.32 0.34 0.36 0.38

fsω=10 kHz I2max

L g= 13

THD i2 = 0.7%

Fig. 14 i2a waveform during steady-state for Lg=0 mH

Vgmax

I2max

Vga

0.06 0.07

-Vgmax

- I2max

0.08 0.09 0.1 0.11 0.12

i2a

L g=0 mH

t (s)

Fig. 15 i2a waveform during steady-state for Lg=13 mH

20kVA Power converter Auto-transformerGrid

Autotransformer

Grid

GcC

S (a,b,c )

L iii L2 Lg2

i2

Vg(a ,b,c) i2(a ,b,c)

V dcLoad

Vdc

V c C ic

- A/D control - Voltage oriented PI control - VR -AD - SVM process

STM32F4 -Discovery

Current and voltage measurement

LCL Filter

ic(a ,b,c)

Lg1

Lg

Grid impedance

A/D board

D/A board

CMOS-15VTTL-3V

High-voltage power circuit

Low -voltage mesurement -control part

LCL Filter

Additional inductances Lg2

Load

STM32F4-Discovery

Measurement board

TTL-CMOS

Fig. 16 Experimental set-up

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Marwa Ben Saïd-Romdhane et al. Systematic design method for PI controller with Virtual Resistor-based Active Damping of LCL filter

5 Experimental results

Fig.16 shows the experimental set-up used to test the VR-AD in order to prove efficiency, robustness as well as performances of the controllers design procedure. This experimental set-up incorporates two main parts: The first one consists in a power part that contains: 1) the grid utility source, 2) an autotransformer to vary grid voltage magnitude, 3) A DC-link capacitor (1100 μF/800 V), 4) a variable resistive load connected to the DC-link capacitor, 5) a 20 kVA three phase high voltage power converter, 6) an LCL filter (three inductors (5 mH/10 A), three capacitors (2 μF/400 V) and three inductors (2 mH/10 A)) and 7) three inductors (4.5 mH/10 A) used to emulate the huge variations of Lg. While the second one consists in a control part that includes: 1) the STM32F4-Discovery, 2) a measurement board, 3) an interface board used to adjust the voltage level between the converter drivers, and 4) the Host PC used in order to configure the STM32F4-Discovery.

The switching frequency and the DC-link reference voltage Vdc

* fixed to 10 kHz and 150 V, respectively,

during experimental tests. As presented in Fig.16, a

supplementary inductance Lg2

of 4.5 mH was inserted in series with L2 in addition to the real inductance Lg

1 that

contains the inductance of the auto-transformer (used during experimental tests) and that of distribution wires. Fig.17 gives the Vdc and i2a waveforms after applying the switching states. It can be shown that the Vdc voltage becomes equal to its reference during steady state. Fig.18 presents the waveforms of Vga and i2a during steady state. According to this figure, Vga and i2a are in phase and therefore a unit power factor operation is attained. Fig.19 gives the waveform of the measured i2a obtained after the application of the switching state for Lg=Lg

1. The obtained measured grid current i2a and its reference value i2a

* are

equal to 1.17A and 1.21A, respectively. Thus, EA is equal to 2.6%. The grid current THD value is equal to 2.9% which satisfies grid code requirements. Fig. 20 presents the steady state response of the measured i2a for Lg= Lg

1+Lg 2.

As depicted in this figure, the system remains stable even for huge variation of Lg. The obtained experimental results are similar to those achieved in simulation by Matlab-Simulink software tool. Moreover, they prove the high performance, robustness and efficiency of the VR-AD and consequently the reliability as well as efficiency of the suggested controllers design procedure.

1) Ch 1: 100 mVolt 250 ms 2) Ch 2: 2 Volt 250 ms

Initial Vdc

Vdc*

i2a

Vdc

Application of the switching states

250 ms

100 V(V dc )

1 A/div(i2a )

L g = L 1g

1＞

2＞

Fig. 17 Response of Vdc and i2a for Lg= Lg 1

1) Ch 1: 500 mVolt 10 ms 2) Ch 2: 2 Volt 10 ms

10 ms 1 A/div

Lg =L 1g

i2 a

Vga

1＞

2＞

Fig. 18 Vga and i2a waveforms for Lg= Lg 1

1) Ch 1: 2 Volt 10 ms

i2

Lg =L 1g + L 2

g

10 ms 1 A/div

1＞

1) Ch 2: 2 Volt 10 ms

L g =L 1g

i2a

10 ms 1 A/div

1＞

Fig. 19 Measured grid current i2a (1 A/div) for Lg= Lg 1

Fig. 20 Measured grid current i2a (1 A/div) for Lg= Lg 1 + L2

g

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Global Energy Interconnection Vol. 1 No. 3 Aug. 2018

6 Conclusion

VR-AD is an efficient solution to mitigate the LCL filter resonance. Nevertheless, filter parameters uncertainties, large grid impedance variation as well as time delay related to digital controllers can significantly endanger the system in terms of stability. To overcome these issues, this paper suggests a systematic and robust procedure for VOC with VR-AD for LCL-GcC that ensures although under the aforementioned restrictions: 1) a sufficient Pm and Gm, 2) a vlow grid current THD value and, 3) a reduced steady-state error EA. Both simulation and experimental results have demonstrated that, based on the proposed tuning procedure, the LCL-GcC can achieve high steady-state performances, high quality of grid current as well as robust stability margins.

Acknowledgements

This work was supported by the Tunisian Ministry of High Education and Research under Grant LSE-ENIT-LR11ES15.

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Biographies

Ilhem Slama-Belkhodja received the Dipl . Ing. and Ph.D. degrees from the Ecole Nationale Supérieure d’Ingénieurs d ’ E l e c t r o t e c h n i q u e d ’ E l e c t r o n i q u e d’Informatique et d’Hydraulique de Toulouse, Toulouse , France, in 1983 and 1985, respectively, and her Doctorat d’Etat from

the Ecole Nationale d’Ingénieurs de Tunis (ENIT) in 1997. She is currently a Full Professor with the Electrical Engineer Department of ENIT, Université Tunis El Manar, Tunisia, and head of research group QehnA from Electrical Systems Laboratory (L.S.E-LR11ES15) of ENIT. Her research interests include fault tolerant electrical systems, power electronics, and control system design related to renewable converters for AC drives, distributed generation and microgrids.

Marwa Ben Said Romdhane was born in 1987 in Tunisia. She received the Ing. and master degrees in electrical engineering from 'Université de Tunis el Manar - Ecole Nationale d'Ingénieurs de Tunis' (UTM-ENIT), Tunis, Tunisia, in 2011 and 2012, respectively, and the Ph.D. degree in electrical engineering from UTM-ENIT in 2016. Her

research interests are focused on the control of grid connected converters with the aim of power quality improvement in micro-grid applications.

Mohamed Wissem Naouar (M’06) was born in Tunisia in 1979. He received the bachelor and master degrees from 'Université de Tunis el Manar - Ecole Nationale d'Ingénieurs de Tunis' (UTM-ENIT), Tunis, Tunisia, in 2003 and 2004, respectively, and the Ph.D. degree from UTM-ENIT and 'Université de Cergy-Pontoise' (UCP), Cergy-Pontoise, France, in

2007, all in electrical engineering. He is currently a Professor at the Electrical Engineer Department of UTM-ENIT, and a scientific researcher in the Electrical Systems Laboratory (L.S.E-LR11ES15). His research interests include digital control of power converters for microgrid applications and power quality improvement.

(Editor Zhou Zhou)