Ece 4121 Lec06_static Cmos

8/4/2019 Ece 4121 Lec06_static Cmos

http://slidepdf.com/reader/full/ece-4121-lec06static-cmos 1/28

ECE4121 Static CMOS Logic.1 ZALAM

VLSI Design

Static CMOS Logic

[Adapted from Rabaey’s Digital Integrated Circuits , ©2002, J. Rabaey et al.]




Review: CMOS Process at a Glance

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

One full photolithographysequence per layer(mask)

Built (roughly) from thebottom up

4 metal2 polysilicon3 source and drain diffusions

1 tubs (aka wells, active areas)

exception!




CMOS Circuit StylesStatic complementary CMOS - except during switching,output connected to either V DD or GND via a low-resistance path

high noise margins- full rail to rail swing- VOH and V OL are at V DD and GND, respectively

low output impedance, high input impedanceno steady state path between V DD and GND ( no static power

consumption)delay a function of load capacitance and transistor resistancecomparable rise and fall times (under the appropriate transistorsizing conditions)

Dynamic CMOS - relies on temporary storage of signalvalues on the capacitance of high-impedance circuitnodes

simpler, faster gatesincreased sensitivity to noise




Static Complementary CMOS

VDD

F(In 1,In2,…In N)

In1In2

InN

In1In2

InN

PUN

PDN

PUN and PDN are dual logic networks

Pull-up network (PUN) and pull-down network (PDN)

PMOS transistors only

pull-up: make a connection from V DD to Fwhen F(In 1,In2,…In N) = 1

NMOS transistors only

pull-down: make a connection from F toGND when F(In 1,In2,…In N) = 0




Threshold Drops

VDD

VDD → 0PDN

0 → VDD

CL

CL

PUN

VDD

0 → VDD - VTn

CL

VDD

VDD

VDD → |VTp |

CL

S

D S

D

VGS

S

SD

D

VGS


http://slidepdf.com/reader/full/ece-4121-lec06static-cmos 6/28ECE4121 Static CMOS Logic.7 ZALAM

Construction of PDN

NMOS devices in series implement a NAND function

NMOS devices in parallel implement a NOR function

A

B

A • B

A BA + B



Dual PUN and PDN

PUN and PDN are dual networksDeMorgan’s theorems

A + B = A • B [!(A + B) = !A • !B or !(A | B) = !A & !B]

A • B = A + B [!(A • B) = !A + !B or !(A & B) = !A | !B]

a parallel connection of transistors in the PUN corresponds to aseries connection of the PDN

Complementary gate is naturally inverting (NAND,

NOR, AOI, OAI)Number of transistors for an N-input logic gate is 2N



CMOS NAND

A

B

A • B

A B

A B F

0 0 1

0 1 1

1 0 1

1 1 0

AB



Complex CMOS Gate

OUT = !(D + A • (B + C))

D

A

B C

D

A

B

C



Standard Cell Layout Methodology

signals

Routingchannel

VDD

GND

What logic function is this?



OAI21 Logic Graph

C

A B

X = !(C • (A + B))

B

AC

i

j

j

VDDX

X

i

GND

AB

C

PUN

PDNABC




OAI22 Logic Graph

C

A B

X = !((A+B)•(C+D))

B

A

D

VDDX

X

GND

AB

C

PUN

PDN

C

D

D

ABCD




OAI22 Layout

BA D

VDD

GND

C

X

Some functions have no consistent Euler path like

x = !(a + bc + de) (but x = !(bc + a + de) does!)




Stick Diagrams

Contains no dimensionsRepresents relative positions of transistors

In

Out

V DD

GND

Inverter

A

Out

V DD

GND B

NAND2




OAI22 Logic Graph

C

A B

X = (A+B)•(C+D)

B

A

D

C

DX

VDD

X

GND

AB

C

PUN

PDN

D

ABCD




A simple method for finding the optimum gate ordering is the Euler-path method: Simply

find a Euler path in the pull-down network graph and a Euler path in the pull-up networkgraph with the identical ordering of input labels, i.e., find a common Euler path for bothgraphs. The Euler path is defined as an uninterrupted path that traverses each edge(branch) of the graph exactly once. Figure 3.12 shows the construction of a commonEuler path for both graphs in our example.




VTC is Data-Dependent

A

B

F= A • B

A B

M1

M2

M3 M4

Cint

VGS1 = VB

VGS2 = VA –VDS1

0

1

2

3

0 1 2

A,B: 0 -> 1B=1, A:0 -> 1A=1, B:0->1

0.5 μ /0.25 μ NMOS

0.75 μ /0.25 μ PMOS

The threshold voltage of M 2 is higher than M 1 due to thebody effect ( γ)

VTn2 = VTn0 + γ(√(|2 φF| + V int) - √|2 φF|)since V SB of M2 is not zero (when V B = 0) due to the presence of C int

VTn1 = VTn0

D

DS

S

weakerPUN




Static CMOS Full Adder Circuit

B

B B

B B

B

B

B

A

A

A

A

A

A A

A

C in

C in

C in

Cin

C in

!Cout !Sum

!Cout = !C in & (!A | !B) | (!A & !B)

Cout = C in & (A | B) | (A & B)

!Sum = C out & (!A | !B | !C in) | (!A & !B & !C in)

Sum = !C out & (A | B | C in) | (A & B & C in)




Next Time: Pass Transistor Circuits

B

A A B

Ece 4121 Lec06_static Cmos

Documents

Transcript of Ece 4121 Lec06_static Cmos