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2004, Copeland Electronics, Inc. CE-188A Datasheet

CE-188A

Features

? 16 bit x86 compatible CPU ? High speed CAN interface option? 512KB Flash ? In-circuit programmable GAL option? 128KB SRAM ? 2 PWD inputs? 32 IO lines from CPU ? Single 5V power supply input? 1 RS-232, 1 TTL UART interface ? CEImon Flash loader/development utility? 8 external interrupt inputs ? Small footprint 1.75 X 2.75? 3 16-bit timer/counters

Applications

? Global Embedded applications ? Security Systems? Point-of-sale terminals ? Remote monitoring & control? Industrial control systems ? Remote telemetry and SCADA? Vending & gaming machines ? OEM applications

Functional Description

The CE-188A is a complete, low cost, single board computer. The high performance, 16 bit x86 compatible processor makes software development fast and easy. The CE-188A is perfect for applications requiring a compact,robust and flexible solution.

The CE-188A comes with an on-board monitor utility CEImon. This monitor can be used to read or write virtuallyany memory or IO address location during development. CEImon is also used to load binary images into flash ormanually access memory or IO peripherals. The CE-188A has one RS-232 and one TTL serial port. A completehigh speed CAN option is available.

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Mechanical Outline

Mechanical

The CE-188A module is on an 0.062 thick FR-4 PC board. It is only 1.75 x 2.75.

Due to the low mass of the board and large headers, no retention is required aside from the sockets. A pair ofmounting holes are provided to insure retention in high shock or vibration environments, if desired.

Power Requirements

Power Supply: 5V 5%

Current: Maximum (with CAN option): 260 mAMaximum (standard): 130 mAPower save mode (CAN option): 40 mAPower save mode (standard): 30 mA

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Header pin connections

Power / CAN / RS-232J4 contains all of the critical IO to supply power to and communicate with the CE-188A. The optional high speedCAN controller IO is also on this header.

13579

2468

10

J4

RS-232/CAN/Power

VCCTXD0B#

CAN_TERM0GND

CANL

RXD0B#

CANHCAN_TERM1GND

Memory Bus

J1 brings out the full address and data bus of the CE-188A. A male vertical header may be populated on non-flash boards for rapid firmware development. In this configuration, an ALPTEX IE ROM emulator may be directlyconnected to the CE-188A. Contact CEI for options and availability.

NOTE: Do not connect pins 1, 2, 3, 4, 23 and 34. They are for emulator use only.

GND 1

A202

VCC 3

A194 A185

A166

A177

A158 A149

A1210

A1311

A712

A813

A614

A915

A516

A1117

A418

OE# 19

A320

A1021

A222

CE# 23

A124

D7 25

A026

D6 27

D0 28

D5 29

D1 30

D4 31

D2 32

D3 33

GND 34

J1

Memory Bus

VCC

VCC

A5 A4 A3 A2 A1 A0

UCS#

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

A12 A11 A10 A9 A8 A7 A6

A14 A13

RD#

A16 A15

A18 A17

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IO and Auxiliary connections

J2 contains alternative power connections, programmable IO, chip selects and other processor features. Pins 34, 38or 49 are reserved for future use. Do not connect anything to these pins. Pins 2 though 6 are not connected on theCE-188A. The CE-188A requires a single 5V power supply. Note that some of the IO pins are connected to twolocations on the header. This is to maintain compatibility with other CEI single board computers. To use the signalas a chip select, pins 45 through 48. To use these signals as IO, connect them to the pins below 31. CSOUT1#,CSOUT2# and CSOUT3# are available only on CAN models.

P6

CSOUT3#

P4

CSOUT1#CSOUT2#

VCC +5V1

-5V 2

+3.3V3

-3.3V 4

+12V5

-12V 6

ALE7

ADEN 8

PA09

PA1 10

PA211

PA3 12

PA413

PA5 14

PA615

PA7 16

PB017

PB1 18

PB219

PB3 20

PB421

PB5 22

PB623 PB7 24PC0

25PC1

26

PC227

PC3 28

PC429

PC5 30

PC631

PC7 32

PD033

PD1 34

PD235

PD3 36

PD437

PD5 38

PD639

PD7 40

INT041

INT1 42

INT243

INT3 44

PCS0#45

PCS1# 46

PCS2#47

PCS3# 48

RDY49

GND 50

J2

IO and Control

P5

ADEN# ALEP22

P10P13P26P23P20

P14P2P19P17

P24P0

WR#

P17P19INT3INT0

P25P1P11P12P21

P15P3P18

P16

RES#RD#

P16P18INT1NMI

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Memory Map

During boot, CEImon uses SRAM for configuration and boot options. Once the processor has been initialized andcontrol is passed to the user application at 0x80000, all SRAM is available to the application.

Memory Map:

F0000 FFFFF CEImon80000 EFFFF FLASH20000 7FFFF Available00000 1FFFF SRAM

If the CAN model is ordered, the SJA1000 CAN controller base address is at IO address 0x0000. Otherwise, the IO bus is completely available for user access.

IO Memory Map:

FF00 FFFF AM186ES peripheral registers0100 FEFF Available for user applications0000 00FF (optional) CAN 2.0B

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Getting Started

The CE-188A is designed with rapid development in mind. No software is required to test new IO or memory basedIO peripherals. CEImon allows the user to read or write virtually any memory or IO address. To access CEImon,start a terminal emulator at 19,200 baud, 8 data bits, 1 stop bit, no parity and no flow control.

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While Holding down the - key on the keyboard, reset or cycle power to the CE-188A. CEImon looks for a ---input on its RS-232 port to boot into the monitor application. If the input is not detected within about 1 second,CEImon will attempt to jump to the user application at address 0x80000.

Pressing the Enter key at the CE> will display the list of available commands. See CEImon Command Referencelater in this document.

At the CE> prompt you can read or write most IO or memory locations.

Care should be taken when changing IO configuration, serial port or any SRAM memory location as they may causethe system to crash. If this happens, reset or cycle power to the CE-188A as described at the beginning of thissection.

CEImon pre-configures the Flash and SRAM chip selects automatically. There is no need to reinitialize thoseregisters in your application.

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CEImon Command Reference

IOWRITE

- Writes a single byte to the specified IO address.

IOREAD

- Reads a single byte to the specified IO address.

WRITE

- Writes a single byte to the specified memory address.

READ

- Reads the specified number of bytes from the specified memory address.

FWRBYT

- Writes a single byte to the specified Flash address.

FERRALL

- Erases all unprotected sectors in the flash. CEImon resides in a protected sector and cannot be erased.

FDEVCOD

- Returns the flash manufactures device code.

FMANCOD

- Returns the flash manufactures code.

FSECER

- Erases the specified flash sector. The top sector in the CE-188A is protected and cannot be erased.

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Programming

Programming the CE-188A is simple and straight forward. CEImon sets up the Flash and SRAM chip selects before jumping to user code. Any compiler capable of creating a binary image may be used to create applications. Thedevelopment kit is shipped with a special version of the HiTech Pacific C compiler with ROM extensions.

Creating a project using UltraEdit-32

1. Select Project -> New Project from the menu and name it CE-188A.2. At the Project window, click Open.3. Create a new file and save it as CE-188A.C.4. Select Project -> Files/Settings.5. Select Add File and add CE-188A.C to the project.6. Add MAIN.C, SIO.C and SIO.H from the Demo directory to the project in the same way.7. Click Open to get back to the project page.8. On the left side of the window, change from Open Files to Project Files. This will show all of the files

associated with the project.9. Go to Advanced->Select Compiler. Select Pacific C, Application, then click OK.10. Go to Advanced->Project Settings.11. Change Target and Command Line Arguments to .bin extensions. They default to .exe.12. Change Output Type to Binary.13. Change ROM Code to yes.14. Change the ROM Address to 80100.15. Change Reset Address to 80000.16. Change Processor Type to 80186.17. Set the Memory Model to large.18. Last, change Build Mode to Release Mode.19. Select View->Views/Lists->Output Window.

Click OK.

To build the project, simply go to Advanced->Build or Advanced->Rebuild All. Once complete, the output windowshould display something similar the following:

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FreeLoader

Now that youve designed and debugged your hardware using CEImon ROM monitor from the previous section,your ready to start writing and debugging your application software. This is where FreeLoader comes in.FreeLoader is used to download a binary image into the CE-188As flash memory.

FreeLoader is a Windows utility for loading binary images into the CE-188A. The utility is simple and straightforward to use:

1. Connect the serial RS-232 port on the CE-188A to a serial port on a PC.2. Start the FreeLoader utility software.3. Select the binary image to load.4. From the menu, set the serial port, and set the baud rate to 19200 baud.5. Click the Load Flash button.6. Connect power or reset the CE-188A.

When the utility completes, the new application will be loaded and ready to go. Simply reset the CE-188A to runyour application.

If at any time during the download you want to break out, press .

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Processor Information

The CE-188A is based on the high performance RDC8830 processor. The RDC8830 is pin compatible with theAM188ES (80x188) processor running at 40MHz. This section does not provide all information on the processor, but is intended to provide information on features supported by the CE-188A. Refer to the RDC8830 datasheet foradditional information.

Processor Release Level

This register defines the processor manufacturer and version.

Processor Release Level Register Address: 0xFFF4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Processor Release

Level 1 1 0 1 1 0 0 1

Read Only Register specifying the processor release level and manufacturer identity

Bits15-8 Processor Version

0x01 = version A: 0x02 = version B: 0x03 = version C

Bit 7-0 Manufacturer IdentityD9 = RDC01 = AMD

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Auxiliary Connection Register

This register defines the programmable pins that are not associated with the Programmable IO (PIO) module. Besure to set bits 3 through 0 to 0 for the CE-188A.

Auxiliary Connection Register Address: 0xFFF2Reset Value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved ENRX1 RTS1 ENRX0 RTS0 LSIZ MSIZ IOSIZ

Read Only Register specifying the processor release level and manufacturer identity

Bit15 - 7 Reserved

Bit6 ENRX1 Enable Receiver request for Serial port 1.

1 = CTS1/ENRX1 set to ENRX10 = CTS1/ENRX1 set to CTS1

Bit5 RTS1 Enable Request to Send of Serial port 1

1 = RTR1/RTS1 set to RTS10 = RTR1/RTS1 set to RTR1

Bit4 ENRX0 Enable Receiver request for Serial port 0

1 = CTS0/ENRX0 set to ENRX00 = CTS0/ENRX0 set to CTS0

Bit3 RTS0 Enable Request to Send of Serial port 0

1 = RTR0/RTS0 set to RTS00 = RTR0/RTS0 set to RTR0

Bit2 LSIZ Set to 0

Bit1 MSIZ Set to 0

Bit0 IOSIZE Set to 0

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Power Save Control Register

This register defines the power save configuration. The MCS0# setting is also embedded in this register. WhenPSEN is set to 1, the processor clock is divided by the value in F2-F0. The processor then continues to run at theslower clock rate. This reduces power consumption and heat dissipation, which can reduce power supply costs andsize as well as improve battery life in portable systems.

NOTE: Clock dependent devices will need to be reprogrammed for the clock frequency changes.

Power Save Control Register Address: 0xFFF0Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PSEN MCSB 0 0 0 1 0 1 0 0 0 0 0 F2 F1 F0

Bit 15 PSENEnable Power SaveModeThis bit is cleared by hardware when an external interruptoccursSoftware interrupts do not change thisbit.1 = Enable Power save and divide the internal clock by the value in F2-F0.

Bit 14 MCSBMCS0# controlbit.0 = MCS0# operates normally1 = MCS0# is active over the entire MCSx#Range

Bit 13-11 Reserved

Bit 10 Reserved Set to 1 for normal operation

Bit 9 Reserved

Bit 8 Reserved Set to 1 for normal operation

Bit 7-3 Reserved

Bit 2-0 F2 - F0 Clock Divisor Select.

F2 F1 F0 ---DivideFactor

0 0 0 --- Divide by 10 0 1 --- Divide by 20 1 0 --- Divide by 40 1 1 --- Divide by 8

1 0 0 ---

Divide by

161 0 1 ---

Divide by32

1 1 0 ---Divide by64

1 1 1 ---Divide by128

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Watchdog Register

A Watchdog timer is used to make sure the processor hasnt crashed or become stuck in a loop. When enabled, theuser software must periodically reset the Watchdog by writing the following sequence to address 0xFFE6:

0x33330xCCCC

This sequence must also be written before writing the watchdog register. To read from the Watchdog timer register,the following sequence must be written:

0x55550xAAAA

The current count should be reset before modifying the Watchdog timer timeout period to ensure that an immediatetimeout does not occur. CEImon disables the Watchdog timer at reset.

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Watchdog Timer Control Register Address: 0xFFE6Reset Value:

0xC08015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ENA WRST RSTF NMIF RES COUNT

Bit15 ENA

Enable WatchdogTimer1 = Enable Watchdogtimer0 = Disable Watchdogtimer

Bit14 WRST

WatchdogReset1 = WDT generates a system reset when the WDT timeout count is reached.0 = WDT generates an NMI interrupt when WDT timeout count is reached if

theNMIF bit is 0. If the NMIF bit is 1, the WDT will generate a system reset upontimeout.

Bit13 RSTF

ResetFlagWhen the watchdog timer reset event has occurred, hardware will set this bit to 1.This bit will be cleared by any keyed sequence write to this register or externalreset. This bit is 0 after external reset or 1 after watchdog timer reset.

Bit12 NMIF

NMIFlag

After the watchdog generates an NMI interrupt, this bit will be set to 1 by hardware.This bit is cleared by any keyed sequence write to thisregister.

Bit 11-8 Reserved

Bit 7-0 COUNT Timeout CountThe COUNT settings determine the duration of the watchdog timer timeout interval.Duration = 2Exponent /FrequencyThe Exponent of the COUNTsetting:Bit 7 -Bit 00 0 0 0 0 0 0 0 N/Ax x x x x x x x 10x x x x x x 1 0 20

x x x x x 1 0 0 21x x x x 1 0 0 0 22x x x 1 0 0 0 0 23x x 1 0 0 0 0 0 24x 1 0 0 0 0 0 0 251 0 0 0 0 0 0 0 26

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Auxiliary Chip Select Register

This register controls the MCS# and PCS# chip selects.

PCS# and MCS# Auxiliary Register Address:0xFFA8Reset Value:-----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1M6 -M0 EX MS 1 1 1 R2 R1 R0

Bit15 Reserved

Bit 14 - 8 M6 - M0MCS# BlockSizeThis determines the total block size for the MCS3# - MCS0# chip selects.Each chip select is active for one quarter of the total block size

M6-M0

TotalBlockSize

MCSx# AddressActive Range

0000001b 8k 2k0000010b 16k 4k0000100b 32k 8k0001000b 64k 16k0010000b 128k 32k0100000b 256k 64k1000000b 512k 128k

Bit7 EX

PinSelector

This bit configures the multiplexed output which the PCS6# and PCS5# pins as chip selects or A2-A11 = PCS6# and PCS5# are configured as peripheral chip select pins.0 = PCS6# is configured as address bit 2, PCS5# is configured as address bit 2.

Bit6 MS Memory or I/O Space selector

1 = PCSx# pins are active for memory bus cycle.0 = PCSx# pins are active for I/O bus cycle.

Bit 5-3 Reserved

Bit2 R2 Ready Mode. This bit configures the ready/wait state enable/disable feature.

1 = External ready ignored.0 = External ready is required.

Bit 1 - 0 Wait States Wait State valueR1 R0 --- Waits0 0 --- 00 1 --- 11 0 --- 21 1 --- 3

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Peripheral Chip Select Register

The PCS# outputs assert with the same timing as the multiplexed address bus. Each peripheral chip select assertsover a 256 byte address range. PCS4# is not available on the CE-188A.

Peripheral Chip Select Register Address:0xFFA4Reset Value:-----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0BA19-BA14 1 1 1 R3 R2 R1 R0

Bit 15 -7

BA19-BA11 Base Address. Corresponds to address bits 19-11 of the address bus.

of the PCS# peripheral chip select block.When the PCS# chip selects are mapped to I/O space, BA19 - BA16 mustbe set to 0000b.

Bit 14 -8 M6 - M0 MCS# Block Size

This determines the total block size for the MCS3# - MCS0# chip selects.Each chip select is active for one quarter of the total block size

M6-M0

TotalBlockSize

MCSx# AddressActive Range

0000001b 8k 2k0000010b 16k 4k0000100b 32k 8k0001000b 64k 16k0010000b 128k 32k0100000b 256k 64k1000000b 512k 128k

Bit7 EX Pin Selector

This bit configures the multiplexed output which the PCS6# and PCS5# pins as chip selects or A2-A11 = PCS6# and PCS5# are configured as peripheral chip select pins.0 = PCS6# is configured as address bit 2, PCS5# is configured as address bit 2.

Bit6 MS Memory or I/O Space selector

1 = PCSx# pins are active for memory bus cycle.0 = PCSx# pins are active for I/O bus cycle.

Bit 6-4 Reserved

Bit 3, 1-0 Wait State value

Wait State valueR3 R1 R0 --- Waits0 0 0 --- 00 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 5

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1 0 1 --- 71 1 0 --- 91 1 1 --- 15

Bit2 R2 Ready Mode. This bit configures the ready/wait state enable/disable feature.

1 = External ready ignored.0 = External ready is required.

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Interrupt Controller

The RDC8830 processor can receive interrupts from internal and external sources. The processor hardwarearranges the priority of these signals.

There are up to eight external interrupt sources on the RDC8830. Five maskable interrupt pins (INT6, INT5, INT3,INT1,INT0) and one nonmaskable interrupt (NMI) pin. There are eight internal interrupt sources that are notconnected to external pins. They are used for the three timers, two DMA channels, two serial ports, and thewatchdog timer NMI. INT 5 and INT 6 are multiplexed with DRQ0 and DRQ1 respectively. They are available ifthe DMA is not enabled or is being used with internal synchronization.

INT3, INT1 and INT0 can be either edge or level triggered. INT6 and INT5 are edge triggered only. An externalinterrupt controller can be used as the system master by programming the internal interrupt controller to operate inslave mode. INT6-INT4 are not available in this mode.

Interrupts are automatically disabled when an interrupt is taken. Interrupt-service routines may re-enable interrupts by setting the IF flag. This allows interrupts of greater or equal priority to interrupt the currently executing ISR.Interrupts from the same soured are disabled as long as the corresponding bit in the interrupt in-service register isset.

Interrupt Type

An 8-bit interrupt type identifies each of the 256 possible interrupts.

Software exceptions, internal peripherals, and non-cascaded external interrupts supply the interrupt type through theinternal interrupt controller.

Interrupt Vector Table

The interrupt vector table is a memory area of 1 Kbyte beginning at address 0x00000 that contains up to 256 four- byte memory address pointers to interrupt handlers for each interrupt type. For each interrupt, and 8-bit interrupttype identifies the interrupt vector table entry.

Interrupts 0x00 to 0x1F are reserved.

Maskable and Nonmaskable Interrupts

A maskable interrupt is an interrupt that can be configured to be ignored. This does not mean that the interruptevent does not occur, or that it is not set in the flags register. It means that the interrupt handler is not called whenthe event is called.

Interrupt types 0x08 through 0x1F are maskable. Of these, only 0x08 through 0x14 are in use.

There is a period of time when writing the interrupt mask register that all interrupts may be temporarily be enabled.This can cause an interrupt to occur in spite of them being masked. Always disable interrupts before writing theinterrupt mask register to avoid masked interrupts from being accepted.

The only interrupts that cannot be masked are the NMI and software interrupts. These are serviced regardless of theinterrupt enable status.

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Interrupt Handling

When an interrupt is requested, the controller determines if it is enabled (not masked) and that there are no higher priority interrupts being serviced or pending.

When a valid interrupt is requested, the interrupt controller jumps to a 4-byte vector in the interrupt vector table.The vector table is available in the first 1K of memory space (0x0000 to 0x003FF). The vector is used to jump tothe location in memory of the program that will service the interrupt.

More information on interrupts is available in the RDC8830 datasheet.

Interrupt Registers

Following are the registers that control the function of the interrupt signals.

Serial Port 0 Interrupt Control Register Address: 0xFF44Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved 1 MSK PR2 PR1 PR0

(Master Mode)

Bit 15 - 4 Reserved

Bit3 MSK Mask

1 = Mask the interrupt source for asynchronous serial port 0.0 = Enable Serial Port 0 interrupt.

Bit 2 - 0 PR2-PR0 Priority. These bits determine the priority of the serial port relative to other interrupt

sources.Priority Selection:PR2 PR1 PR0 --- Priority

0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

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Serial Port 1 Interrupt Control Register Address: 0xFF42Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved 1 MSK PR2 PR1 PR0

(Master Mode)

Bit 15 - 4 Reserved

Bit3 MSK Mask

1 = Mask the interrupt source for asynchronous serial port 1.0 = Enable Serial Port 1 interrupt.

Bit 2 - 0 PR2-PR0 Priority. These bits determine the priority of the serial port relative to other interruptsources.Priority Selection:PR2 PR1 PR0 --- Priority

0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

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DMA 1 / INT6 Interrupt Control Register Address: 0xFF36Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0

(Master Mode)

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for DMA1.0 = Enable DMA1 interrupt.

Bit 2 - 0 PR2-PR0 Priority. These bits determine the priority of the serial port relative to other interruptsources.Priority Selection:

PR2 PR1 PR0 --- Priority0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

(Slave Mode), Reset value: 0x0000

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for DMA 1.0 = Enable DMA 1 interrupt.



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DMA 0 / INT5 Interrupt Control Register Address: 0xFF34Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0

(Master Mode)

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for DMA0.0 = Enable DMA0 interrupt.




Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for DMA 0.0 = Enable DMA 0 interrupt.



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Timer Interrupt Control Register Address: 0xFF32Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00 0 0 0 0 0 0 0 0 0 0 0 MSK PR2 PR1 PR0

(Master Mode)

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for the timer controller.0 = Enable the timer controller interrupt.




Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for the timer controller.0 = Enable the timer controller interrupt.



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INT 3 Control Register Address: 0xFF3EReset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved ETM LTM MSK PR2 PR1 PR0

(Master Mode)

Bit 15-8,6-5 Reserved

Bit 7 ETM Edge-Trigger Enable. When this bit is set to 1 and bit 4 is set to 0, interrupt istriggered on the low to high edge.

Bit 4 LTM Level-triggered Mode.1 = Interrupt is triggered by high active level.0 = Interrupt is triggered by low to high edge.

Bit 3 MSK Mask1 = Mask the interrupt source for INT3.0 = Enable INT3 interrupt.


PR2 PR1 PR0 --- Priority0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 4

1 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

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INT 2 Control Register Address: 0xFF3CReset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved ETM LTM MSK PR2 PR1 PR0

(Master Mode)

Bit 15-8,6-5 Reserved





PR2 PR1 PR0 --- Priority0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 4

1 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

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INT 1 Control Register Address: 0xFF3AReset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved ETM SFNM C LTM MSK PR2 PR1 PR0

(Master Mode)

Bit 15-8 Reserved


Bit 6 SFNM Special Fully Nested Mode, Set to 1 to enable.

Bit 5 C Cascade Mode. Set to 1 to enabled Cascade mode for INT0 or INT1.




PR2 PR1 PR0 --- Priority0 0 0 --- 0 High

0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

(Slave Mode), This register is for timer 2 interrupt control. Reset value: 0x0000

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for timer 2.0 = Enable timer 2 interrupt.


PR2 PR1 PR0 --- Priority0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 2

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0 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

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INT 0 Control Register Address: 0xFF38Reset Value:0x000F

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved ETM SFNM C LTM MSK PR2 PR1 PR0

(Master Mode)

Bit 15-8 Reserved


Bit 6 SFNM Special Fully Nested Mode, Set to 1 to enable.

Bit 5 C Cascade Mode. Set to 1 to enabled Cascade mode for INT0 or INT1.




PR2 PR1 PR0 --- Priority0 0 0 --- 0 High

0 0 1 --- 10 1 0 --- 20 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

(Slave Mode), This register is for timer 1 interrupt control. Reset value: 0x0000

Bit 15-4 Reserved

Bit 3 MSK Mask1 = Mask the interrupt source for timer 1.0 = Enable timer 1 interrupt.


PR2 PR1 PR0 --- Priority0 0 0 --- 0 High0 0 1 --- 10 1 0 --- 2

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0 1 1 --- 31 0 0 --- 41 0 1 --- 51 1 0 --- 61 1 1 --- 7 Low

Interrupt Status Register Address: 0xFF30Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DHLT 0 0 0 0 0 0 0 0 0 0 0 MSK TMR2 TMR1 TMR0

(Master Mode)

Bit 15 DHLT DMA Halt

1 = Halts any DMA activity. When non-maskable interrupts occur.0 = When an IRET instruction is executed.

Bit 14-3 Reserved

Bit 2 - 0TMR2-TMR0 1 = corresponding timer has an interrupt request pending.


Bit 15 DHLT DMA Halt1 = Halts any DMA activity. When non-maskable interrupts occur.0 = When an IRET instruction is executed.

Bit 14-3 Reserved

Bit 2 - 0TMR2-TMR0 1 = corresponding timer has an interrupt request pending.

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Interrupt Request Register Address: 0xFF2EReset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved SP0 SP1 I4 I3 I2 I1 I0 D1/I6 D0/I5 Res TMR

(Master Mode)The interrupt request register is a read-only register. For internal interrupts (SP0, SP1, D1/I6, D0,I5, TMR).The corresponding bit is set to a 1 when a device requests an interrupt. The bit is reset during internallygenerated interrupt acknowledge. The INT4-INT0 bits reflect the current value of the external signal (I4-I0).

Bit 15-11 Reserved

Bit 10 SP0 Serial Port 0 Interrupt request.

Bit 9 SP1 Serial Port 1 Interrupt request.

Bit 8-4 I4-I0 Interrupt Requests1 = corresponding INT pin has an interruptpending.

Bit 3-2 D1/I6-D0/I5 DMA channel or INT interrupt request1 = corresponding DMA channel or INT pin has an interrupt pending.

Bit 1 Reserved

Bit 0 TMR Timer Interrupt request.1 = The timer control unit has an interrupt requestpending.

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In-Service Register Address: 0xFF2CReset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved SP0 SP1 I4 I3 I2 I1 I0 D1/I6 D0/I5 Res TMR

(Master Mode)The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in theregister is cleared by writing the corresponding interrupt type to the EOI register.

Bit 15-11 Reserved

Bit10 SP0 Serial Port 0 Interrupt in-service.

1 = the serial port 0 interrupt is currently being serviced.

Bit 9 SP1 Serial Port 1 Interrupt in-service.1 = the serial port 1 interrupt is currently being serviced.

Bit 8-4 I4-I0 INT Interrupt in-service.1 = the corresponding INT interrupt is currently being serviced.

Bit 3-2 D1/I6-D0/I5 DMA channel or INT interrupt in-service.1 = the corresponding DMA or INT interrupt is currently being serviced.

Bit 1 Reserved

Bit 0 TMR Timer Interrupt in-service.1 = the Timer interrupt is currently being serviced.

In-Service Register Address: 0xFF2CReset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TMR2 TMR1 D1 D0 Res TMR0

(Slave Mode)The bits in the INSERV register are set by the interrupt controller when the interrupt is taken. Each bit in theregister is cleared by writing the corresponding interrupt type to the EOI register.

Bit 15-6 Reserved

Bit 5-4 TMR2-TMR1 Timer2, Timer1 interrupt in-service

1 = the corresponding TMR interrupt is currently being serviced.

Bit 3-2 D1/I6-D0/I5 DMA channel or INT interrupt in-service.1 = the corresponding DMA or INT interrupt is currently being serviced.

Bit 1 Reserved

Bit 0 TMR0 Timer 0 Interrupt in-service.1 = the Timer 0 interrupt is currently being serviced.

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Priority Mask Register Address: 0xFF2AReset Value: 0x0007

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 PRM2 PRM1 PRM0

(Master Mode)Determines the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 Reserved

Bit 2-0PRM2-PRM0 Priority Field Mask. Determines the minimum priority required for a maskable

Interrupt source to generate an interrupt.

Priority PR2 PR1 PR0(High)

0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 0

(Low) 7 1 1 1

(Slave Mode)Determines the minimum priority level at which maskable interrupts can generate an interrupt.

Bit 15-3 Reserved

Bit 2-0PRM2-PRM0 Priority Field Mask. Determines the minimum priority required for a maskable

Interrupt source to generate an interrupt.

Priority PR2 PR1 PR0(High)

0 0 0 01 0 0 12 0 1 03 0 1 14 1 0 05 1 0 16 1 1 0

(Low) 7 1 1 1

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Interrupt Mask Register Address: 0xFF28Reset Value:0x07FD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved SP0 SP1 I4 I3 I2 I1 I0 D1/I6 D0/I5 Res TMR

(Master Mode)

Bit 15-11 Reserved

Bit10 SP0 Serial Port 0 Interrupt Mask.

The state of the interrupt mask bit for serial port 0.

Bit 9 SP1 Serial Port 1 Interrupt Mask.The state of the interrupt mask bit for serial port 1.

Bit 8-4 I4-I0 Interrupt MasksIndicates the state of the interrupt mask of the corresponding INT interrupt.

Bit 3-2 D1/I6-D0/I5 DMA Channel or INT MasksIndicates the state of the interrupt mask of the corresponding DMA channel or INTinterrupt.

Bit 1 Reserved

Bit 0 TMR Timer Interrupt Mask.The state of the mask bit of the timer control unit.

Interrupt Request Register Address: 0xFF28Reset Value:0x003D

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TMR2 TMR1 D1/I6 D0/I5 Res TMR0

(Slave Mode)

Bit 15-6 Reserved

Bit 5-4 TMR2-TMR1 Timer 2 / Timer 1 Interrupt Mask.The state of the mask bit of the Timer Interrupt Control Register.

1 = Timer 2 / Timer 1 interrupt requests are masked.

Bit 3-2 D1/I6-D0/I5 DMA Channel or INT MasksIndicates the state of the interrupt mask of the corresponding DMA channel or INT interrupt.

Bit 1 Reserved

Bit 0 TMR0 Timer0 Interrupt Mask.Indicates the state of the interrupt mask of Timer 0.

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Poll Status Register Address: 0xFF26Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IREQ Reserved S4 S3 S2 S1 S0

(Master Mode)The Poll Status (POLLST) register mirrors the current state of the Poll register. The POLLST can beread without affecting the current interrupt request.

Bit 15 IREQ Interrupt Request.1 = Interrupt pending. S4 - S0 contain valid data.

Bit 14-5 Reserved

Bit 4-0 S4-S0 Poll StatusIndicates the Interrupt type of the highest priority pending interrupt.

End-Of-Interrupt Address: 0xFF22Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NSPEC Reserved S4 S3 S2 S1 S0

(Master Mode)

Bit 15 NSPEC Non-specific EOI1 = indicates non-specific EOI0 = indicates specific EOI type in S4-S0

Bit 14-5 Reserved

Bit 4-0S4-S0 EOI Source Type

Specifies the EOI interrupt currently being processed.

End-Of-Interrupt Address: 0xFF22Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 L2 L1 L0

(Slave Mode)

Bit 15-3 Reserved

Bit 2-0 L2-L0 Interrupt Type.Encoded value indicating the priority of the interrupt service bit to reset. Writesto these bits cause an EOI to be issued for the interrupt type in slave mode.

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Interrupt Vector Register Address: 0xFF20Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 T4 T3 T2 T1 T0 0 0 0

(Slave Mode)

Bit 15-8 Reserved

Bit 7-3 T4-T0 Interrupt Type.Sets the five most significant bits of the interrupt types for the internal interrupt type.Interrupt typeTimer 2 interrupt controller T4,T3,T2,T1,T0,1,0,1Timer 1 interrupt controller T4,T3,T2,T1,T0,1,0,0DMA 1 interrupt controller T4,T3,T2,T1,T0,0,1,1DMA 0 interrupt controller T4,T3,T2,T1,T0,0,1,0

Timer 0 interrupt controller T4,T3,T2,T1,T0,0,0,0

Bit 2-0 Reserved

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DMA Controller

DMA (Direct Memory Access) allows transfer of data between memory and peripherals without the CPUsinvolvement. The CE-188A has two independent DMA controllers. DMA sources can come from the serialchannels, timer 2 or an external DRQ source.

The DMA controller needs to know from where the transfer is coming, to where it is going, how many bytes totransfer and how (increment, decrement or neither for both from and to addresses). More information is available inthe RDC8830 datasheet.

DMA Control Registers

DMA0 Address: 0xFFCAReset Value:0xFFF9

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM/IO DDEC DINC SM/IO SDEC SINC T C INT SYN1 SYN0 P TDRQ Res CHG ST B/W

DMA1 Address: 0xFFDAReset Value:0xFFF9

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DM/IO DDEC DINC SM/IO SDEC SINC T C INT SYN1 SYN0 P TDRQ Res CHG ST B/W

Bit 15 DM/IO Destination Address Space Select.1 = The destination address is in memory space.0 = The destination address is in IO space.

Bit 14 DDEC Destination Decrement.1 = The destination address automatically decrements after each transfer.The B/W bit determines the decrement value by 1 or 2.When both DDEC and DINC are 1, the address is constant.0 = Disable the decrement function.

Bit 13 DINC Destination Increment.1 = The destination address automatically increments after each transfer.The B/W bit determines the increment value by 1 or 2.0 = Disable the increment function.

Bit 12 SM/IO Source Address space select.1 = The source address is in memory space.0 = The source address is in IO space.

Bit 11 SDEC Source decrement.1 = The source address is decremented after each transfer.The B/W bit determines the decrement value by 1 or 2. The address remainsconstant when both SDEC and SINC bits are set to 1.0 = Disable the decrement function.

Bit 10 SINC Source increment.1 = The source address is incremented after each transfer.The B/W bit determines the increment value by 1 or 2. The address remains

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constant when both SDEC and SINC bits are set to 1.0 = Disable the increment function.

Bit 9 TC Terminal Count.1 = The synchronized DMA transfer is terminated when the DMA transfer countregister reaches 0.0 = The synchronized DMA transfer is not terminated when the DMA transfer countregister reaches 0.Unsychronized DMA transfers always terminat when the transfer count reaches 0.

Bit 8 INT Interrupt1 = DMA unit generates an interrupt request when the transfer count completes.The TC bit must also be set to generate an interrupt.

Bit 7 SYN1-SYN0 Synchronization TypeSyn1 Syn0 --- Synchronization Type

0 0 -- - Unsynchronized

0 1 --- Source Synchronized1 0 --- Destination Synchronized1 1 -- - Reserved

Bit 5 P Priority1 = Selects high priority for this channel when both DMA channels are intransfer at the same time.

Bit 4 TDRQ Timer Enable / Disable Request1 = Enable the DMA requests for Timer 2.0 = Disable the DMA requests for Timer 2.

Bit 3 Reserved

Bit 2 CHG Changed Start Bit. This bit must be set to 1 to modify the ST bit.

Bit 1 ST Start/Stop DMA channel1 = Start the DMA channel.0 = Stop the DMA channel.

Bit 0 B/W Byte / Word Select1 = The address is incremented or decremented by 2 after each transfer.0 = The address is incremented or decremented by 1 after each transfer.

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DMA Transfer Count Register

DMA0 Address: 0xFFC8Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0

DMA1 Address: 0xFFD8Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 DMA Transfer count. The value of this register is decremented by 1 after each transfer.

DMA Destination Address High Register

DMA0 Address: 0xFFC6Reset Value: - ---

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedDDA19-DDA16

DMA1 Address: 0xFFD6Reset Value: - ---

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedDDA19-DDA16

Bit 15-4 Reserved

Bit 3 - 0 DDA19-DDA16 High DMA Destination Address. These bits are driven onto A19-A16 duringthe write phase of a DMA transfer.

DMA Destination Address Low Register


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DDA15 -

DDA0


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DDA15 -

DDA0

Bit 15-0DDA15-DDA0 Low DMA Destination Address. These bits are mapped to A15 - A0 during

a DMA transfer. The Value of DDA19-DDA0 will increment ordecrementby 2 after each DMA transfer.

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DMA Destination Address High Register


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedDSA19 -DSA16


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ReservedDSA19 -DSA16

Bit 15 - 4 Reserved

Bit 3 - 0 DSA19-DSA16 High DMA source address. These bits are mapped to A19-A16 duringa DMA transfer when the source address is in memory or IO space.If the source address is in IO space (64kbytes), these bits must be set to0000b.

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DMA Source Address Space Low


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DSA15 -

DSA0


15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0DSA15 -

DSA0

Bit 15-0DDA15-DDA0 Low DMA Source Address. These bits are mapped to A15 - A0 during

a DMA transfer. The Value of DSA19-DSA0 will increment or decrement

by 2 after each DMA transfer.

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Timer Controller

The CE-188A has 3 16-bit programmable timers. Timers 0 and 1 are programmable and connected to external pins(input and output for each timer). These can be used to count or time external events. They may also be used togenerate waveforms.

Timer 2 is used for real-time coding and time-delay applications. It can also be used as a prescale to timers 0 or 1 ora DMA request source.

Timer 0, Timer 1 Mode / Control RegisterTimer 0 Address: 0xFF56

Reset Value: 0x000015 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN ENH INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT

Timer 1 Address: 0xFF5EReset Value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EN ENH INT RIU 0 0 0 0 0 0 MC RTG P EXT ALT CONT

Bit15 EN Enable Bit

1 = Timer isenabled.0 = Timer counter isdisabledThe ENH bit must be set to 1 while writing the EN bit. The ENH and EN bits must bemodified at the sametime.

Bit14 INH Inhibit BitThis bit allows selective writing to the EN bit. The INH bit must be set to 1 during awriteto the EN bit. Both must be modified at the same time. This bit is not stored and isalways read as 0.

Bit13 INT Interrupt Bit

1 = An interrupt request is generated when the count register equals the maximum count.If the timer is configured in dual-max count mode, an interrupt is generated each timethecount reaches max count A or max count B.0 = Timer will not issue an interruptrequest.

Bit12 RIU

Register In UseBit1 = The max count Compare of the Timer is being used.0 = The max count Compare A register of the Timer is beingused.

Bit 11-6 Reserved

Bit 5 MC Maximum Count BitWhen the timer reaches its maximum count, the MC bit will be set to 1 by the

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hardware.

In dual maxcount mode, this bit is set each time either Maxcount Compare A orMaxcount Compare B register is reached. This bit is set regardless of the EN bit.

Bit 4 RTG Re-triggering bitThis bit defines the control function by the input signal of the TMRIN1 pin. When EXT = 1,this bit is ignored1 = Timer Count Register counts internal events. Rising edge triggered.0 = Low input holds the Timer Count Register value. High input enablescounting.

EXT RTG --- Setting

0 0 ---Timer counts internal events if TMRINx pin ishigh.

0 1 ---Timer counts internal events with the count being reset on rising edge ofTMRINx pin.

1 X --- TMRINx pin input acts as a clock source and Timerx Count Registerincreases once for every four external clock cycles.

Bit 3 P PrescalarThis bit and EXT define the timer clock source.EXT P --- Setting

0 0 ---Timer count register increases once for every four internal processorclocks.

0 1 ---Timer count register increases with prescale using timer2.

1 X --- TMRIN1 pin acts as an input acts as clock source and the count registerincreases once four every four external clocks.

Bit 2 EXT External Clock Bit1 = Timer clock source isexternal.0 = Timer clock source isinternal.

Bit 1 ALTAlternate CompareBit.This bit controls whether the timer runs in single or dual maximum count mode.1 = Specifies dual maximum count mode. In this mode the timer counts to Maxcount Compare AThen resets the count register to 0. Then the timer counts to Maxcount Compare B, then resetsthe count register to 0 again and starts over with Maxcount Compare A.0 = Specify single maximum count mode. In this mode the timer will count to the valuecontained in Maxcount Compare A and reset to 0. Maxcount Compare B is not used.

Bit 0 CONT Continuous Mode Bit1 = Sets the timer to run continuously.0 = The timer will halt after counting to the maximum count and the EN bit will becleared.

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Timer 0, Timer 1 Count RegisterTimer 0 Address: 0xFF50

Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Timer 1 Address: 0xFF58Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 Timer Count ValueThis register contains the current timer count. The count is incremented by oneevery four internal processor clocks or prescaled by timer 2, or by one every fourexternal clocks from the TMRIN1 signal.

Timer 0 / 1 Max Count Compare A Register

Timer 0 Address: 0xFF52Reset Value: - ---

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Timer 1 Address: 0xFF5AReset Value: - ---

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 Timer Compare A Value

Timer 0 / 1 Max Count Compare B Register

Timer 0 Address: 0xFF54Reset Value: - ---

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Timer 1 Address: 0xFF5C

Reset Value: - ---15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 Timer Compare B Value

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Timer 2 Mode / Control Register Address: 0xFF66Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0EN ENH INT 0 0 0 0 0 0 0 MC 0 0 0 0 CONT

Bit 15 ENEnableBit1 = EnableTimer 20 = Timer 2 counterinhibit.The ENH bit must be set to 1 when writing the EN bit and must be done during the samewrite.

Bit 14 ENH Inhibit BitThis bit allows selective update to the EN bit.

Bit 13 INTInterruptBit1 = An interrupt request is generated when the count register equalsmaximum count.0 = Timer 2 interrupt disabled.

Bit 12-6 Reserved

Bit 5 MC Maximum Count BitWhen the timer reaches it's maximum count, this bit is set to 1 by thehardware. Thisbit is set regardless of the EN bit state.

Bit 4 - 1 Reserved

Bit 0 CONT Continuous mode bit1 = Timer continues to run after it reaches maximumcount.0 = The EN bit is cleared and the timer is held after each timer countreaches themaximumcount.

Timer 2 Count Register Address: 0xFF60Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 Timer 2 Count ValueThis register contains the current count of timer 2. The count is incremented byone every 4 clock cycles.

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Timer 2 Maxcount Compare Register Address: 0xFF62Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0


Bit 15-0 TC15-TC0 Timer Compare A Value

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Asynchronous Serial Controller

The CE-188A has two independent asynchronous serial channels. They provide full-duplex, bidirectional datatransfer using standard communications protocols. Asynchronous port 0 is available. Asynchronous port 1 is RS-232 compliant. Asynchronous port 1 is also used by CEImon to download new application firmware and for userdebug.

These ports support:

? Full-duplex operation? 7, 8 or 9 bit data transfers? Odd, even or no parity? Short or long break characters? Parity, Framing and overrun error detection? Hardware handshaking (serial 0 only)

? DMA transfers to and from? Interrupt support? Independent baud rate generators? Double buffered transmit and receive buffers

Flow Control

Serial port 0 supports hardware flow control. The flow control signals (RTS0#/RTR0#) are configurable bysoftware to support different protocols.

DCE/DTE Protocol

The DCE/DTE protocol provides flow control. This protocol provides flow control where one serial port is the

receiver and the other a transmitter. In this protocol, the DTE device sends data. When data is available to send theDTE asserts the RTS# signal. The DCE sees this as a request to enable its receiver. The DCE signals the DTEdevice that its ready to receive data by asserting RTR#. The DTE cannot signal the DCE that it is ready to receivedata and the DCE cannot signal that it is ready to send data.

To configure for this protocol, ENRX bit should be set and the RTS bit should be cleared. To implement the DTEdevice the ENRX bit should be cleared and the RTS bit should be set. These bits are located in the AUXCONregister.

CTS/RTR Protocol

This protocol is the most common form of hardware flow control. It provides flow control in both directions. Whena port is ready to receive data, the port asserts the RTR# signal. The other port will not send data until its CTS#signal is asserted. To enable this protocol, clear both the ENRX and RTS bits for the serial port. This is the defaultconfiguration.

Asynchronous Serial Registers

Following is a list of registers for both Asynchronous Serial channels. Note that serial channel 1 does not supporthardware flow control and is used for RS-232 only.

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Serial Port Control Register

Serial Port

0 Address: 0xFF80Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMA RISE BRK TB8 FC TXIE RXIE TMOD RMOD EVN PE MODE

Serial Port1 Address: 0xFF10

Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMA RISE BRK TB8 FC TXIE RXIE TMOD RMOD EVN PE MODE

Bit 15-13 DMADMA ControlField.These bits configure the serial port for use with DMA transfersBit15

Bit14

Bit13 Receive Transmit

0 0 0NO

DMA NO DMA0 0 1 DMA 0 DMA 10 1 0 DMA 1 DMA 00 1 1 N/A N/A1 0 0 DMA 0 NO DMA1 0 1 DMA 1 NO DMA

1 1 0NO

DMA DMA 0

1 1 1NO

DMA DMA 1

Bit12 RSIE Receive status interrupt enable

1 = Enable serial port interrupt enable.

Bit11 BRK

SendBREAK1 = Drive TXD pin low.Long Break = TXD driven low for greater than (2M * 3) bit times.Short Break = TXD driven low for greater than M bit times.*M = start bit + data bits number + parity bit + stop bit

Bit10 TB8 Transmit Bit 8

This bit is transmitted as the ninth data bit in modes 2 and 3. This bit is cleared

after each transmission.

Bit 9 FC Flow Control Enable1 = Enable hardware flow control0 = Disable hardware flow control

Bit 8 TXIE Transmitter Ready Interrupt EnableWhen the transmit holding register is empty (THRE in status register), aninterrupt occurs.1 = Enable

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Interrupt0 = DisableInterrupt

Bit 7 RXIE Receive Data Ready Interrupt EnableWhen the receive buffer is full (RDR in status register), an interrupt occurs.1 = EnableInterrupt0 = DisableInterrupt

Bit 6 TMOD Transmit Mode1 = Enables the transmit section of the UART0 = Disables the transmit section of the UART

Bit 5 RMOD Receive Mode1 = Enables the receive section of the UART0 = Disables the receive section of the UART

Bit 4 EVNEvenParityThis bit is valid only when the PE bit is set.1 = Even parity checking enforced.0 = Odd parity checking enforced.

Bit 3 PE Parity Enable1 = Enable parity checking.0 = Disable paritychecking.

Bit 2-0 MODMode ofOperation

Bit 2Bit1

Bit0 Mode Data Bits Parity

StopBits

0 0 1 1 7 or 81 or

0 10 1 0 2 9 N/A 1

0 1 1 3 8 or 91 or

0 11 0 0 4 7 N/A 1

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Serial Port Status Register

Serial Port

0 Address: 0xFF82Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Res


Reset Value: ----15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved BRK1 BRK0 RB8 RDR THRE FER OER PER TEMT HS0 Res

Bit 15-11 Reserved

Bit 10 BRK1 Long Break Detected1 = Long Break Detected

Bit 9 BRK0 Short Break Detected1 = Short Break Detected

Bit 8 RB8 Received Bit 8This bit should be reset by software.This bit contains the ninth data bit received in modes 2 and 3.

Bit 7 RDR Received Data Ready. Read Only.1 = The received data register contains valid data.This bit can only be reset by reading the Receive Register.

Bit 6 THRE Transmit Hold Register Empty. Read only.1= The transmit register is ready to accept data.This bit is reset by writing data to the transmit register

Bit 5 FER Framing Error Detected1 = Framing error detected.This bit must be reset by software.

Bit 4 OER Overrun Error Detected1 = Overrun error detected.This bit must be reset in softare.

Bit 3 PER Parity Error Detected1 = Parity Error Detected (mode 1 and 3).This bit must be reset in software.

Bit 2 TEMP Transmitter Empty. Read Only.1 = Transmit shift register is empty

Bit 1 HS0 Handshake Signal. Read only.This bit reflects the inverted value of the CTS# pin.

Bit 0 Reserved

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Serial Port Transmit Register

SerialPort 0 Address: 0xFF84

Reset Value: ----15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TDATA


Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TDATA

Bit 15-8 Reserved

Bit 7-0 TDATA Transmit DataData written to this register is transmitted out the serial channel.

Serial Port Receive Register


Reset Value: ----

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RDATA


Reset Value: ----15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RDATA

Bit 15-8 Reserved

Bit 7-0 RDATA Received DataThe RDR bit should be read as 1 before reading the RDATA register.

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Serial Port Divisor Register

Serial Port

0 Address: 0xFF88Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BAUDDIV


Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BAUDDIV

Bit 15-0 BAUDDIVBaud RateDivisorThe general formula for the baud rate divisor is:Baud Rate = Processor Clock / (16 * BAUDDIV)

Supported Baud Rates

The serial ports can operate at different baud rates.

NOTE: If power-save mode is enabled, the baud rate divisor must be reprogrammed to reflect the new processorclock frequency. Also, since power-save is exited automatically when an interrupt is taken, serial port transmit andreceive data may be corrupted if the serial port is in use and interrupts are enabled in power-save mode.

The formula for determining the baud rate is as follows:

BAUDDIV = (Processor Frequency (16 baud rate))

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Divisor atProcessor ClockRate

BaudRate

20 MHz 40MHz300 4116 8333600 2083 41661050 1190 23801200 1041 2083180 694 13882400 520 10414800 260 5207200 173 3479600 130 26019200 65 130

28800 43 8638400 33 6556000 22 4557600 22 4376800 16 32115200 10 22128000 9 19153600 5 16

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Programmable I/O

The CE-188A has 24 available IO pins. Each of these pins may be programmed as an IO signal if the specialfunction of the pin is not needed. Each pin may be programmed as an input or output, with or without pull-up or pull-down resistors. These may also be used as an open-drain output. Below is a list of IO signals and theyre useon the CE-188.

PIO Function Reset Status CE-188A Use0 TMRIN1 Input with 10K pullup -1 TMROUT1 Input with 10K pulldown -2 PCS6#/A2 Input with 10K pullup -3 PCS5#/A1 Input with 10K pullup -4 DT/R Normal Operation, Input with 10K pullup -5 DEN# Normal Operation, Input with 10K pullup -

6 SRDYNormal Operation, Input with 10Kpulldown -

7 A17 Normal Operation, Input with 10K pullup A178 A18 Normal Operation, Input with 10K pullup A189 A19 Normal Operation, Input with 10K pullup A19

10 TMROUT0 Input with 10K pulldown -11 TMRIN0 Input with 10K pullup -12 DRQ0/INT5 Input with 10K pullup -13 DRQ1/INT6 Input with 10K pullup -14 MCS0# Input with 10K pullup -15 MCS1# Input with 10K pullup -16 PCS0# Input with 10K pullup CAN / Available17 PCS1# Input with 10K pullup -18 PCS2#/CTS1#/ENRXQ# Input with 10K pullup -19 PCS3#/RTS1#/RTR1# Input with 10K pullup -20 RTS0#/RTR0# Input with 10K pullup -21 CTS0#/ENRX0# Input with 10K pullup -22 TXD0 Input with 10K pulldown -23 RXD0 Input with 10K pulldown -24 MCS2# Input with 10K pullup -25 MCS3#/RFSH# Input with 10K pullup -26 UZI# Input with 10K pullup -27 TXD1 Input with 10K pullup TXD28 RXD1 Input with 10K pullup RXD29 S6/CLKDIV# Input with 10K pullup Reserved

30 INT4 Input with 10K pullupCANInt/Reserved

31 INT2 Input with 10K pullup Reserved

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PIO Mode Registers

This and the direction register determine whether each pin is a function, or is en abled as an IO signal. Each bit inthese registers represent a PIO pin.

PIO 1 Mode Register Address: 0xFF76Reset Value:0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMODE (31 - 16)

Bits 15-0 PMODE31-16 PIO Mode Bit

The definition of the PIO pins are configured by a combination of PIO Mode and PIODirection. Each PIO pin is programmed individually

Mode Dir Pin Definition0 0 --- Normal Operation0 1 --- PIO Input with Pullup/Pulldown1 0 --- PIO Output1 1 --- PIO Input without Pullup/Pulldown

PIO 0 Mode Register Address: 0xFF70Reset Value: 0x0000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMODE (15 - 0)

Bits 15-0 PMODE 15-0 PIO Mode Bit

The definition of the PIO pins are configured by a combination of PIO Mode and PIODirection. Each PIO pin is programmed individually

Mode Dir Pin Definition0 0 --- Normal Operation0 1 --- PIO Input with Pullup/Pulldown1 0 --- PIO Output1 1 --- PIO Input without Pullup/Pulldown

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PIO Direction Registers

This field determines if the specified IO is an input or output. A 1 defines the specified pin as an input, and a 0defines the pin as an output.

PIO 1 Direction Register Address: 0xFF78Reset Value:0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDIR (31 - 16)

Bits 15-0 PDIR31-16 PIO Direction Register1 = Configure PIO pin as an input.0 = Configure PIO pin as anoutput.

PIO 0 Direction Register Address: 0xFF72Reset Value:0xFFFF

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDIR (15 - 0)

Bits 15-0 PDIR15 - 0 PIO Direction Register1 = Configure PIO pin as an input.0 = Configure PIO pin as anoutput.

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PIO Data Registers

If a pin is defined as an output, the value of the corresponding bit in the data register is driven on the pin. If the pinis defined as an input, the pin state is reflected in this register.

PIO 1 DataRegister Address: 0xFFFA

Reset Value: ----15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDATA (31 - 16)

Bits 15-0PDATA31-16 PIO Data Bits

These bits map to PIO31-PIO16 and indicate the value driven when the PIO pinisprogrammed as an output or reflects the external level when read.

PIO 0 DataRegister Address: 0xF74

Reset Value: ----15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PDATA (15 - 0)

Bits 15-0PDATA 15-0 PIO Data Bits

These bits map to PIO15-PIO0 and indicate the value driven when the PIO pin isprogrammed as an output or reflects the external level when read.

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Revision Information

Revision 1.0

? Initial Release

Warranty

All CEI products are covered against defects in manufacturing for a period of 30 days from date of purchase.

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Contact Information

Copeland Electronics, Inc. 440 Colony PlaceGahanna, OH 43230Tel: (614) 475-1690Fax: (614) 882-6062

Email: [email protected] Internet: www.copelandelectronics.com

Legal

Information contained in this publication regarding device applications and the like is intended through suggestiononly and may be superseded by updates. It is your responsibility to ensure that your application meets with yourspecifications. No representation or warranty is given and no liability is assumed by Copeland Electronics,Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual

property rights arising from such use or otherwise. Use of Copeland Communications products as criticalcomponents in life support systems is not authorized . Copeland Electronics, Inc. does not guarantee its products

CE-188A Datasheet 101304

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