ALSTOM Observer Report Vfinal

8/11/2019 ALSTOM Observer Report Vfinal

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1

Z1 Z2 Z3 Z4

Z1 Z4

Z2 Z3


10/43

Z1 Z2

Z3 Z4

Vcc

D1

D3

D2

D4

qr

Cr Lr

r

qw

Cw

Lm

mA B

Rr

TR

qL

CL Load

Z1 Z2

Z3 Z4

Vcc

D1

D3

D2

D4

qr

Cr Lr

r

qw

Cw

Lm

mA B

Rr

TR

qL

CL Load


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x(t) = (J(s) R)Dx(t) + BuAB(t)

J(s) =

0 0 0 10 0 0 1 s2I0 0 0 sI1 (1 s2I) sI 0

, R=

0 0 0 00 0 0 00 0 0 00 0 0 Rr

B=

0001

s = {1, 0, 1}

x(k+ 1) = Fx(k) + GuAB(k) + K[y(k) Cx(k)]

F= G= K= y(k)=Cx(k)=

(ur) (uw) (ul) (ir)

ul uw ir J(s)R A0 A1


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2

Physical System Output

1

Fr_Phy

x' = Ax+Bu

y = Cx+Du

State-SpaceMultiport

Switch

In1Out1

Logic Unit

K*u

D

-K-

B

Add

K*u

A1

K*u

A0

K*u

A-1

1

Uab

A1 D M

M=diag(Cr Cw Cl Lr)

ur uw ul ir

D A0 A1 A1 gama0 phi0 gama1 phi1 gama1 phi1


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Fr_Obs

1

Discrete Observer Output

K*u

phimin1

K*u

phi1

K*u

phi0

K*u

gamamin1

K*u

gama1

K*u

gama0

Multiport

Switch

In1Out1

Logic Unit

K*u

K_C

y(n)=Cx(n)+Du(n)

x(n+1)=Ax(n)+Bu(n)

Discrete State-Space

K*u

D

Add4

Add3

Add2

Add1

Add

2

Fr_Phy

1

Uab

Discrete Observer

2


1


Uab

Fr_Phy


Uab

Fr_Phy

Physical Syst em Output

Physical System

Uab

Controller


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0 1 2 3 4 5 6

x 10-4

-150

-100

-50

0

50

100

150

200Physical System

Time(sec)

Ur(V)

Uw(V)Ul(V)

Ir(A)

0 1 2 3 4 5 6

x 10-4

-150

-100

-50

0

50

100

150

200Discrete Observer

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)

Uab


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0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

x 104

-50

0

50

100Xilinx Observer Model Output

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

x 104

-50

0

50

100Discrete Observer Model Output

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)


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5

Xilinx Observer Output

4

ir

3

ul

2

uw

1

ur

sel

d1(min1)

d1(0)

d1(1)

d2(min1)

d2(0)

d2(1)

d3(min1)

d3(0)

d3(1)

d4(min1)

d4(0)

d4(1)

ur

uw

ul

Fr

switch

Uab

x1

x2

x3

x4

gamamin1

Uab

x1

x2

x3

x4

gama1

Uab

x1

x2

x3

x4

gama0

a1

a2

a3

a4

x1

x2

x3

x4

Phimin1

a1

a2

a3

a4

x1

x2

x3

x4

Phi1

a1

a2

a3

a4

x1

x2

x3

x4

Phi0

uw

ul

ir

Out1

Logic Unit

Gateway Out3

Gateway Out2

Gateway Out1

Gateway Out

Gateway In1

Gateway In

In1

In2

In3

In4

ur

uw

ul

Fr

Discrete State Space

a1

a2

a3

a4

ur

uw

ul

ir

D

Fr_Phy

Fr_Obs

K_C

Adjustment

a

b

a + b

Add3

In1

In2

In3

In4

In5

In6

In7

In8

Out1

Out2

Out3

Out4

Add2

In1

In2

In3

In4

In5

In6

In7

In8

Out1

Out2

Out3

Out4

Add1

In1

In2

In3

In4

In5

In6

In7

In8

Out1

Out2

Out3

Out4

Add

System

Generator

2

Uab

1 Fr_Phy


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Discrete Observer

3

Xili nx Observer Output

2


1


Fr_Phy

Uab


Xili nx ObserverUab

Fr_Phy

Discret e Observ er Output

Uab

Fr_Phy


Physical System

Uab

Controller

0 5 10 15 20 25 300

20

40

60

80

100

120

140

160

180

200Xilinx Observer Wordlength Calculation

Decrease in Wordlength

Maximumd

ifferencebetweenPhysicalsystemandObserver

Ur(V)Uw(V)

Ul(V)

Ir(A)


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Tscaling = diag(2xUr 2xUw 2xUl 2xIr ) xUr , xUw , xUl xIr

2

xUr Ur

Ur2

xUr

= 1log(Ur) + xUr log(2)=log(1)xUr log(2) =log(Ur)xUr=log(Ur)/log(2)

Tscaling

Tscaling

x(k+ 1)=F x(k) + Gu(k)

y(k) = Cx(k) + Du(k)

xscaled(k+ 1)=T F T1x(k) + T Gu(k)

yscaled(k) = C T1x(k)+Du(k)

xscaled(k+ 1)=Tx(k+ 1)=T F T1x(k) + T Gu(k)+T K[y(k)yscaled(k)]

yscaled(k)=Ty(k) = C T1x(k)+Du(k)


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y(k)

xscaled(k+ 1)=Tx(k+ 1)=T F T1x(k) + T Gu(k)+T K[y(k)yscaled(k)]

xscaled(k+ 1)=Tx(k+ 1)=T F T1x(k) + T Gu(k)+T K[Cx(k) + Du(k) CT1x(k) Du(k)]

xscaled(k+ 1)=Tx(k+ 1)=T F T1

x(k) + T Gu(k)+T K[Cx(k) CT1

x(k)]xscaled(k+ 1)=Tx(k+ 1)=T F T

1x(k) + T Gu(k)+TKCT1[T x(k)x(k)]

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

x 104

-1

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4x 10

-3 States of Unscaled Observer

Time(sec)

Ur(V)

Uw(V)Ul(V)

Fr(Wb)

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

x 104

-1.5

-1

-0.5

0

0.5

1States of Scaled Observer

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Fr(Wb)


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0 5 10 15 20 25 300

20

40

60

80

100

120

140

160

180

Decrease in Wordlength

Maximumd

ifferencebetweenPhysicalsystemandObserver

Scaled Xilinx Observer Wordlength Calculation

Ur(V)

Uw(V)

Ul(V)

Ir(A)


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0 1 2 3 4 5 6

x 104

-1

-0.5

0

0.5

1

1.5

2

2.5

3Error (Xilinx observer at F=25 MHz)

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)

0 1 2 3 4 5 6

x 104

-2

0

2

4

6

8

10Error (Xilinx observer at F=80 MHz)

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)


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uw

0 1 2 3 4 5 6

x 10-4

-1

0

1

2

3

4

5Error

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)

0 1 2 3 4 5 6

x 10-4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4Error

Time(sec)

Ur(V)

Uw(V)

Ul(V)

Ir(A)


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ur= 0, uw = 0, ul = 0, ir = 0 ur = 0, uw = 0, ul= 0, ir= 0

ur= 50, uw = 0, ul= 300, ir = 20 ur = 50, uw= 0, ul = 300, ir= 20

ur= 0, uw = 0, ul = 300, ir= 0 ur = 0, uw = 0, ul= 300, ir = 0


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1

Xilinx Ob server Output

sel

d1(min1)

d1(0)

d1(1)

d2(min1)

d2(0)

d2(1)

d3(min1)

d3(0)

d3(1)

ur

ul

Fr

switch

Uab

x1

x2

x3

gamamin1

Uab

x1

x2

x3

gama1

Uab

x1

x2

x3

gama0

x 1

Tscaling

a1

a2

a3

x1

x2

x3

Phimin1

a1

a2

a3

x1

x2

x3

Phi1

a1

a2

a3

x1

x2

x3

Phi0

i r O ut 1

Logic Unit

Gateway Out2

Gateway Out1

Gateway Out

Gateway In1

Gateway In

In1

In2

In3

ur

ul

Fr


a1

a2

a3

ur

ul

ir

D

Fr_Phy

Fr_Obs

K_C

Adjustment

a

b

a + b

Add3

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add2

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add1

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add

System

Generator

2

Uab

1 Fr_Phy


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0 1 2 3 4 5 6

x 10

-4

-60

-40

-20

0

20

40

60

80

1003rd Order Scaled Xilinx Observer

Time(sec)

Ur(V)

Ul(V)

Ir(A)

0 1 2 3 4 5 6

x 10-4

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4Error

Time(sec)

Ur(V)

Ul(V)

Ir(A)


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ir ur

ir ur

0 2 4 6 8 10 12

x 104

-2

0

2

4

6

8

10

12

14

16

18

Samples

Error

Ur(V)

Ul(V)

Ir(A)


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R9


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uw


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1


sel

d1(min1)

d1(0)

d1(1)

d2(min1)

d2(0)

d2(1)

d3(min1)

d3(0)

d3(1)

ur

ul

Fr

switch

Uab

x1

x2

x3

gamamin1

Uab

x1

x2

x3

gama1

Uab

x1

x2

x3

gama0

x 1

Tscaling

uab

Square Wave Generator

a1

a2

a3

x1

x2

x3

Phimin1

a1

a2

a3

x1

x2

x3

Phi1

a1

a2

a3

x1

x2

x3

Phi0

i r Out1

Logic Unit

Gateway Out2

Gateway Out1

Gateway Out

In1

In2

In3

ur

ul

Fr


a1

a2

a3

ur

ul

ir

D

cast

Convert1

castConvert

Fr_Phy

Fr_Obs

K_C

Adjustment

a

b

a + b

Add3

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add2

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add1

In1

In2

In3

In4

In5

In6

Out1

Out2

Out3

Add

SystemGenerator


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1

uab

a

b

a0

a

b

a0

a

b

a


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68_67

24_0

59_57

5_5

Gama0/1/min1

Phi0/1/-1

D

Adder Switch AddSub1

Logic Unit

61_60 4

51_50 4

45_374

16 3

1 1

1

7_0

State Space

81_80

85_84 AddSubK_C

4

4

1

11

1

Fr_Phy

Uab

48_47

7_0

59_57

5_5

Gama0/1/min1

Phi0/1/-1

D

Adder Switch AddSub1

Logic Unit

41_40 4

42_40 4

45_37 4

16 3

1 1

1

7_0

State Space

75_74 AddSubK_C

4

4

1

11

1

Fr_Phy

Uab

11_0 Tscaling

72_70

81_80

ALSTOM Observer Report Vfinal

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