MIMOSA22 MIMOSA26 ULTIMATE

MIMOSA22 MIMOSA26 ULTIMATE

Christine HU-GUO (IPHC-Strasbourg)

STAR meeting IPHC [email protected] 215-17/06/2009

MIMOSA22

AMS-OPTO 0.35µm Dim. pixel 18.4 x 18.4 µm² Dim. Matrice 136 x 576 pixels

8 sorties analogiques 128 sorties numériques

Vitesse d’intégration < 100µs Slow Control : JTAG Références internes (DAC) Lecture multiplexée 50 MHz

Non inclus: suppression de zéros

Soumission : octobre 2007 Retour de fonderie : janvier 2008


In Pixel amplification & Signal Processing (1)

4 digital control signals per row: PWR_On, Slct_Row, Slct_Grp, Clamping Slct_Row (16xCK), PWR_On (2x16xCK), Slct_Gr (16x16xCK): power activate

signals Clp: signal for CDS (3xCK)

Slct_Gr

Slct_Row

Slct_Row

Slct_Row

16

pix Slct_Gr

Slct_Row

Slct_Row

Slct_Row

16

pix

16

pix Slct_Gr

Slct_Row

Slct_Row

Slct_Row

Column –level

discriminator

RD

CALIB

LATCH

PWR_On (N)

PWR_On (N+1)

Slct_Row (N)

Slct_Row (N+1)

Slct_Row

Clp

RD

CALIB

LATCH

CK

Pix

leve

lD

isc

rile

ve

l

CK

RD CALIB

Chargesensingelement

RST (optional)

AMP SF

Slct Row

PWR ON

Clamping

Slct Grp

Integrated in Discri.



Common Source (CS) amplification in pixel Only NMOS transistors can be used

1 2 3CS + Reset Improved CS + Reset Improved CS + Feedback + Self biased

out

bias

signal current

M2

M3

M1

reset

Nwell / Pepi

out

bias

signal current

M2

M3

M1

reset

Nwell / Pepi

M4

signal current

Nwell / Pepi

Pdiff / NwellM2

M3

M4M5Low-pass filter

feedback

a negative low frequency feedback

was introduced to decrease

amplification gain variations due to

process variations



Measured Mimosa22 pixel (Amp+CDS) performances (20 °C) before irradiation:

After ionizing irradiation, feedback self-biased structure has the best performances (conditions: +20C, integration time ~92μs)

1

2

3

3

3

2

1

3

2

1 3

2

1

3

2

1

Pixel types Diode size (µm2) CVF* (µV/e-) ENC (e-)

CS + Reset 15.21 57.3 13.3 +/- 0.1

Improved CS + Reset 15.21 57.3 13.0 +/- 0.1

Improved CS + Feedback + self biased 14.62 55.8 12.3 +/- 0.1

BUT from previous studies (MIMOS15) on chips without in-pixel signal processing the noise was in order of ~15e after dose of 1MRad


Increasing Radiation Tolerance in Pixel

Ionizing radiation tolerance (22bis, 22ter): Pixel circuit level:

ELT for the transistor connected to the detection diode

Diode level: Remove thick oxide surrounding N-well

diode by replacing with thin-oxide

Non-ionizing radiation tolerance: Reducing pixel pitch pitch < 20 µm 18.4 µm Increasing sensing diode size: limited by layout Reducing integration time ~100-200 µs

Michal Szelezniak - PhD thesis defense - 25 February 2008

1515

I ncreased tolerance to ionizing radiation

standard diode layoutstandard diode layout

thinthin--oxide diode layoutoxide diode layout

Shot Noise Contribution @ 30Shot Noise Contribution @ 30°°C C and @4 ms integration timeand @4 ms integration time

ENCENCshotshot = 39 electrons= 39 electrons


n+n+p+ n+p-well

depleted region

p++ substrate

passivation

oxide

p-epi

n-well

FOXFOXFOX

n+n+p+p-well

depleted region

p++ substrate

passivationoxide

p-epi

n-well

FOX FOX n+

gnd gnd

n+

Michal Szelezniak - PhD thesis defense - 25 February 2008

1515

I ncreased tolerance to ionizing radiation

standard diode layoutstandard diode layout

thinthin--oxide diode layoutoxide diode layout

Shot Noise Contribution @ 30Shot Noise Contribution @ 30°°C C and @4 ms integration timeand @4 ms integration time



n+n+p+ n+p-well

depleted region

p++ substrate

passivation

oxide

p-epi

n-well

FOXFOXFOX

n+n+p+p-well

depleted region

p++ substrate

passivationoxide

p-epi

n-well

FOX FOX n+

gnd gnd

n+

signal current

Nwell / Pepi

Pdiff / NwellM2

M3

M4M5Low-pass filter

feedback


Column-level discriminators

Discriminator design considerations: Small input signal Offset compensated amplifier stage Dim: 16.4 x 430 µm2

Conversion time = row read out time (~200 ns) Consumption ~230 µW

RDVclp_d

LATCH

RD

RD

CALIB

CALIB

REF1

REF2

To Pixel

Vclp_d

RD

RD

RDLATCH

Q

Q

Column-level Double Sampling (DS) reduce pixel to pixel dispersion (FPN)


Column-level discriminators: characterizations

0.3 mV 0.2 mV

Analyze Method

Scan threshold voltage (N discri.) Fit to an error function Mean Offset Sigma temporal noise (TN)

Mean of N sigma average of TN RMS of N offsets FPN

Resultants

FPN : 0.2 mV TN : 0.3 mV


Mimosa22 test results: Pixels + 128 Discriminators

Test in lab: Temporal Noise:

0.64 mV 11.5 e-

FPN: 0.22 mV 3.9 e-

Beam test with 120 GeV pions at CERN-SPS

Threshold ~ 4 mV 6 σ noise

0.64 mV0.22 mV

Detection efficiency > 99.5% Spatial resolution < 4 µm Fake rate < 10-4


MIMOSA26: 1st Sensor with Integrated Ø

Pixel array: 576 x 1152, pitch: 18.4 µm Active area: ~10.6 x 21.2 mm2

In each pixel: Amplification CDS (Correlated Double Sampling)

1152 column-level discriminators offset compensated high

gain preamplifier followedby latch

Zero suppression logic

Memory management Memory IP blocks

Readout controller JTAG controller

Current Ref. Bias DACs

Row sequencer Width: ~350 µm

I/O PadsPower supply PadsCircuit control PadsLVDS Tx & Rx

Chip size : 13.8 x 21.6 mm2,

AMS C35B4: 0.35µm technology Testability: several test points

implemented all along readout path

Pixels out (analogue) Discriminators Zero suppression transmission

Reference Voltages Buffering for 1152 discriminators

Test blocksPLL, 8b/10b


Readout Chain: Pixel + discriminator

Reference voltages (threshold) & clamping voltage are analogue signals which have to apply to 1152 discriminators

Need stable signals during "RD" & "CALIB" periods Ex. RD (3 CK ~ 30 ns)

Need to drive ~2 cm long line RC distribution line + successive charge rejections

Even an ideal voltage source CANNOT satisfy these requirements 1152 discriminators are divided into 4 groups, 4 bias DAC

compensate process dispersions of discriminators

dis

cri

min

ato

r

dis

cri

min

ato

r

dis

cri

min

ato

r

1152 discriminators

RDVclp_d

LATCH

RD

RD

CALIB

CALIB

REF1

REF2

To Pixel

Vclp_d

RD

RD

RDLATCH

Q

Q

DAC

DAC

DAC

DAC

28

8

dis

cri

min

ato

rsREF

28

8

dis

cri

min

ato

rs

28

8

dis

cri

min

ato

rs

28

8

dis

cri

min

ato

rs


Readout Chain: zero suppression + memories

…………

Col

umn

0

…………A/D

A/D

Sparse Data Scan(N states)



…………Core of the zero suppression

Retaining M states per row (+ addresses) among 18 banks

Memory 0

Memory 1

Serial transmission

Pix

el

Arr

ay

Dis

cri

min

ato

rs

Col

umn

1152

Connected to column-level discriminators outputs Zero suppression is based on row by row sparse data scan

readout and organized in pipeline mode in three steps:


…………

Col

umn

0

…………A/D

A/D

Col

umn

1152







Memory 0

Memory 1

Serial transmission

1st step: 1152 columns terminations 18 banks // scan Based on a sparse data scan algorithm to find hit pixels

(discriminator output = "1") Up to 4 contiguous pixel signals above Vth will be encoded in a

2 bits state word following by address of the 1st pixel Find up to N states with column addresses per bank



State: Column address of the 1st pixel+ 2 bits code

State 1

Row M-1

Row M+1

Row M

0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0Row M

HIT

……

..…

.…

1 0

1 0

0

1

0

0

1 0

1 1

1

1

1

1

State Binary code

00

01

10

11

state

state

state

State 2

0

……

.…

Column address of the 1st pixel

2 bits binary code


…………

Col

umn

0

…………A/D

A/D

Col

umn

1152







Memory 0

Memory 1

Serial transmission

2nd step: Read out the outcomes of the 1st step in all banks and keep up to M

states Add row and bank addresses


…………

Col

umn

0

…………A/D

A/D

Col

umn

1152


…………S0C

olum

n 0

Col

umn

63

…………S1C

olum

n 0

Col

umn

63

…………S17C

olum

n 0

Col

umn

63






Memory 0

Memory 1

Serial transmission

3rd step: Store the outcomes of the 2nd step to a memory The memory is made of 2 IP's buffers continuous read-out

1 buffer stores current frame, 1 buffer is read out previous frame

Serial transmission by LVDS pad

N, M, Memory capacity and Memory Read-out speed depend on hit density

N = 6, M = 9, Memory ~ 40 Kbits, Nominal Read-out Freq.: 80 MHz


Test MIMOSA26 Mimosa26 returned from foundry on February 2009. Extensive tests are going on in the laboratory. Measured temporal noise = 0.6-0.7 mV and FPN = 0.3-0.4 mV for pixel array with its

associated discriminators. These values are equivalent to those obtained with Mimosa22. Figures show measured results for one quarter of the matrix with column-level discriminators.

The remaining three quarters of the matrix exhibit similar performances showing a good uniformity of the whole 576 x 1152 pixels with the 1152 discriminators

The characterization of Mimosa26 will be completed by the beam tests planned in Summer 2009 + yield evaluation

Entries 576 x 288

Mean 0.64 mV

RMS 0.07 mV

Noise distribution [mV] Threshold distribution [mV]

Entries 576 x 288

Mean -0.93 mV

RMS 0.29 mV


MIMOSA26 ULTIMATE

Zero suppression: physics condition : 2,4 x 105 hits/s/cm2

Readout time 200 µs ~ 200 hits/frame/sensor The highest luminosity expected at STAR for RHIC2 gives:

60 hits / cm2 , = 8 hits On the inner layer of sensors in a 200 µs integration window. This rate is for interactions and peripheral collisions. Possible background

sources are not included. ~450 hits /sensor

450 hits + 240 Noisy pixels > 5 & ~2x10-4 noisy pixels

Safety factor ?

1. SUZE design: Maximum output speed: ~100 Mbits/s 2 memories of (200 x 3) x 32 bits

2. With new condition & with ~ 10-4 ~ 100 noisy pixels Zero suppression based on SUZE's group & row hits finders design Points have to be changed:

1. Increase maximum output speed: up to 256 Mbits/s2. Increase dimension of memory: > 3 times larger (2048 x 32)x23. Memory: anti latch up?

530 hits /frame equivalent


Power Consumption

Pixel Pitch

Pixel Discri. DAC Group Hits Finder

Line Hits Finder

Sq. controller

Memory LVDS receiv.

LVDS trans.

Total (mW)

Power (mW/cm2)

18.4 µ 230 mW

0.2 x 1152

350 mW

0.3 x 1152

20 mW 60 mW

15 mW x 4

6 mW 20 mW 34 mW 8 mW 66 mW

(16.5x4)

794 172

500 hits


Frequency distribution Circuit needs:

CK : 80 MHz Pixels & Comparators: 16 CK 5 MHz SUZE CK: 80 MHz LVDS out: 2 x 120 MHz 2 x 160 MHz

Input Freq.: 160 MHz external CK Option: 80 MHz external CK Option: 10 MHz external CK, PLL (N=16) output Freq.: 160 MHz

80 MHz will be made in chip Possibility to integrate 8b/10b encoding to allow reasonable clock recovery

Option for the Ultimate1 chip

PLL (N=16)

10MHz

160MHz

÷ 10

LVDS LVDS

÷ 2

8b/10b Pixels & Comparators

80 MHz16 MHz

LVDS

160MHz


Ultimate Sensor Testing Functionality (implemented in MIMOSA26)

Pixel Array

switch

comparators

switch

switch

SUZE

Inject 2 Test Voltages to emulate pixels outputs

Read One Row Register, Pixels & Comparators are in normal mode, tint = 200µs, Readout freq. = 5 MHz via 2 LVDS output pads. The auto increment functional logic to scan whole matrix will be studied.

Inject 2 SUZE Test Rows

Inject Test Pattern of 32 bits to emulate memory outputs

LVDS

MUX

LVDS

MUX160 MHz

5 MHz 5 MHzswitch

DataLVDS CK

MUX

5 MHz

160 MHz

Analogue pixels outputs


Latch-up

MIMOSA22 MIMOSA26 ULTIMATE

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