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Transcript of lec3Mos
8/9/2019 lec3Mos
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Introduction to
CMOS VLSIDesign
CMOS Transistor Theory
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MOS devicesSlide 2CMOS VLSI Design
Outline
Introduction MOS Capacitor
nMOS I-V Characteristics
pMOS I-V Characteristics Gate and Diffusion Capacitance Pass Transistors
RC Delay Models
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MOS devicesSlide 3CMOS VLSI Design
Introduction
So far, we hae treated transistors as ideal switches !n O" transistor passes a finite a#ount of current
$ Depends on ter#inal olta%es
$ Derie current-olta%e &I-V' relationships Transistor %ate, source, drain all hae capacitance
$ I ( C &∆V)∆t' -* ∆t ( &C)I' ∆V
$ Capacitance and current deter#ine speed
!lso e+plore what a de%raded leel really #eans
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MOS devicesSlide 4CMOS VLSI Design
MOS Capacitor
Gate and .ody for# MOS capacitor Operatin% #odes
$ !ccu#ulation
$ Depletion $ Inersion
polysilicon %ate
&a'
silicon dio+ide insulator
p-type .ody/-
V% 0 1
&.'
/-
1 0 V% 0 Vt
depletion re%ion
&c'
/-
V% * Vt
depletion re%ion
inersion re%ion
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MOS devicesSlide 5CMOS VLSI Design
Terminal Voltages
Mode of operation depends on V%, Vd, Vs
$ V%s ( V% $ Vs
$ V%d ( V% $ Vd
$ Vds ( Vd $ Vs ( V%s - V%d
Source and drain are sy##etric diffusion ter#inals $ 2y conention, source is ter#inal at lower olta%e
$ 3ence Vds ≥ 1
nMOS .ody is %rounded4 5irst assu#e source is 1 too4
Three re%ions of operation $ Cutoff
$ Linear
$ Saturation
V%
Vs Vd
V%dV%s
Vds/-
/
-
/
-
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MOS devicesSlide 6CMOS VLSI Design
nMOS Cutoff
"o channel
Ids ( 1
/-
V%s ( 1
n/ n/
/-
V%d
p-type .ody
.
%
s d
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MOS devicesSlide 8CMOS VLSI Design
nMOS Saturation
Channel pinches off
Ids independent of Vds
6e say current saturates
Si#ilar to current source
/-
V%s * Vt
n/ n/
/-
V%d 0 Vt
Vds * V%s-Vt
p-type .ody
.
%
s d Ids
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MOS devicesSlide 9CMOS VLSI Design
I-V Characteristics
In 7inear re%ion, Ids depends on
$ 3ow #uch char%e is in the channel8
$ 3ow fast is the char%e #oin%8
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MOS devicesSlide 10CMOS VLSI Design
Channel Charge
MOS structure loo9s li9e parallel plate capacitorwhile operatin% in inersion
$ Gate $ o+ide $ channel
:channel (
n/ n/
p-type .ody
/
V%d
%ate
/ /
source
-
V%s
-drain
Vds
channel-
V%
Vs
Vd
C%
n/ n/
p-type .ody
6
7
to+
SiO; %ate o+ide&%ood insulator, εo+ ( <4='
polysilicon%ate
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MOS devicesSlide 11CMOS VLSI Design
Channel Charge
MOS structure loo9s li9e parallel plate capacitorwhile operatin% in inersion
$ Gate $ o+ide $ channel
:channel ( CV
C (
n/ n/
p-type .ody
/
V%d
%ate
/ /
source
-
V%s
-drain
Vds
channel-
V%
Vs
Vd
C%
n/ n/
p-type .ody
6
7
to+
SiO; %ate o+ide&%ood insulator, εo+ ( <4='
polysilicon
%ate
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MOS devicesSlide 12CMOS VLSI Design
Channel Charge
MOS structure loo9s li9e parallel plate capacitorwhile operatin% in inersion
$ Gate $ o+ide $ channel
:channel ( CV
C ( C% ( εo+67)to+ ( Co+67
V (
n/ n/
p-type .ody
/
V%d
%ate
/ /
source
-
V%s
-drain
Vds
channel-
V%
Vs
Vd
C%
n/ n/
p-type .ody
6
7
to+
SiO; %ate o+ide&%ood insulator, εo+ ( <4='
polysilicon
%ate
Co+ ( εo+ ) to+
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MOS devicesSlide 13CMOS VLSI Design
Channel Charge
MOS structure loo9s li9e parallel plate capacitorwhile operatin% in inersion
$ Gate $ o+ide $ channel
:channel ( CV
C ( C% ( εo+67)to+ ( Co+67
V ( V%c $ Vt ( &V%s $ Vds);' $ Vt
n/ n/
p-type .ody
/
V%d
%ate
/ /
source
-
V%s
-drain
Vds
channel-
V%
Vs
Vd
C%
n/ n/
p-type .ody
6
7
to+
SiO; %ate o+ide&%ood insulator, εo+ ( <4='
polysilicon
%ate
Co+ ( εo+ ) to+
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MOS devicesSlide 14CMOS VLSI Design
Carrier velocity
Char%e is carried .y e- Carrier elocity v proportional to lateral >-field
.etween source and drain v (
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MOS devicesSlide 15CMOS VLSI Design
Carrier velocity
Char%e is carried .y e- Carrier elocity v proportional to lateral >-field
.etween source and drain v ( µ> µ called #o.ility
> (
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MOS devicesSlide 16CMOS VLSI Design
Carrier velocity
Char%e is carried .y e- Carrier elocity v proportional to lateral >-field
.etween source and drain v ( µ> µ called #o.ility
> ( Vds)7
Ti#e for carrier to cross channel?
$ t (
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MOS devicesSlide 18CMOS VLSI Design
nMOS Linear I-V
"ow we 9now $ 3ow #uch char%e :channel is in the channel
$ 3ow #uch ti#e t each carrier ta9es to cross
ds I =
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MOS devicesSlide 19CMOS VLSI Design
nMOS Linear I-V
"ow we 9now $ 3ow #uch char%e :channel is in the channel
$ 3ow #uch ti#e t each carrier ta9es to cross
channel
dsQ I
t =
=
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MOS devicesSlide 20CMOS VLSI Design
nMOS Linear I-V
"ow we 9now $ 3ow #uch char%e :channel is in the channel
$ 3ow #uch ti#e t each carrier ta9es to cross
channel
ox 2
2
ds
ds gs t ds
ds gs t ds
Q I t
W V C V V V
L
V V V V
µ
β
=
= − − ÷
= − − ÷
ox=
W C
Lβ µ
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MOS devicesSlide 21CMOS VLSI Design
nMOS Saturation I-V
If V%d 0 Vt, channel pinches off near drain
$ 6hen Vds * Vdsat ( V%s $ Vt
"ow drain olta%e no lon%er increases current
ds I =
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MOS devicesSlide 22CMOS VLSI Design
nMOS Saturation I-V
If V%d 0 Vt, channel pinches off near drain
$ 6hen Vds * Vdsat ( V%s $ Vt
"ow drain olta%e no lon%er increases current
2dsat
ds gs t dsat
V I V V V β = − − ÷
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MOS devicesSlide 23CMOS VLSI Design
nMOS Saturation I-V
If V%d 0 Vt, channel pinches off near drain
$ 6hen Vds * Vdsat ( V%s $ Vt
"ow drain olta%e no lon%er increases current
( )2
2
2
dsat ds gs t dsat
gs t
V I V V V
V V
β
β
= − − ÷
= −
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MOS devicesSlide 24CMOS VLSI Design
nMOS I-V Summary
( ) 2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
V I V V V V V
V V V V
β
β
< = − − < ÷
− >
Shockley @st order transistor #odels
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MOS devicesSlide 25CMOS VLSI Design
Eample
>+a#ple? a 14A µ# process fro# !MI se#iconductor $ to+ ( @11 B
$ µ ( <1 c#;)Vs
$ Vt ( 14E V Plot Ids s4 Vds
$ V%s ( 1, @, ;, <, F,
$ se 6)7 ( F); λ
( )14
2
8
39 885 10350 120 !
100 10ox
W W W C A V
L L Lβ µ µ
−
−
• × = = = ÷ ÷×
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
I d s
& # ! '
V%s (
V%s ( F
V%s ( <
V%s ( ;
V%s ( @
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MOS devicesSlide 26CMOS VLSI Design
pMOS I-V
!ll dopin%s and olta%es are inerted for pMOS Mo.ility µp is deter#ined .y holes
$ Typically ;-<+ lower than that of electrons µn
$ @;1 c#;
)Vs in !MI 14A µ# process Thus pMOS #ust .e wider to proide sa#e current
$ In this class, assu#e µn ) µp ( ;
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MOS devicesSlide 27CMOS VLSI Design
Capacitance
!ny two conductors separated .y an insulator haecapacitance
Gate to channel capacitor is ery i#portant
$ Creates channel char%e necessary for operation
Source and drain hae capacitance to .ody
$ !cross reerse-.iased diodes
$ Called diffusion capacitance .ecause it is
associated with source)drain diffusion
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MOS devicesSlide 28CMOS VLSI Design
!ate Capacitance
!ppro+i#ate channel as connected to source C%s ( εo+67)to+ ( Co+67 ( Cper#icron6
Cper#icron is typically a.out ; f5)µ#
n/ n/
p-type .ody
6
7to+
SiO; %ate o+ide
&%ood insulator, εo+ ( <4=ε1'
polysilicon
%ate
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MOS devicesSlide 29CMOS VLSI Design
Diffusion Capacitance
Cs., Cd.
ndesira.le, called parasitic capacitance Capacitance depends on area and peri#eter
$ se s#all diffusion nodes $ Co#para.le to C%
for contacted diff
$ H C% for uncontacted
$ Varies with process
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MOS devicesSlide 30CMOS VLSI Design
"ass Transistors
6e hae assu#ed source is %rounded 6hat if source * 18
$ e4%4 pass transistor passin% VDD
VDD
VDD
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MOS devicesSlide 31CMOS VLSI Design
"ass Transistors
6e hae assu#ed source is %rounded 6hat if source * 18
$ e4%4 pass transistor passin% VDD
V% ( VDD
$ If Vs * VDD-Vt, V%s 0 Vt
$ 3ence transistor would turn itself off
nMOS pass transistors pull no hi%her than VDD-Vtn
$ Called a de%raded @ $ !pproach de%raded alue slowly &low Ids'
pMOS pass transistors pull no lower than V tp
VDD
VDD
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MOS devicesSlide 32CMOS VLSI Design
"ass Transistor C#ts
VDD
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
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MOS devicesSlide 33CMOS VLSI Design
"ass Transistor C#ts
VDD
VDD V
s
( VDD
-Vtn
VSS
Vs ( V
tp
VDD
VDD-Vtn VDD-Vtn
VDD
-Vtn
VDD
VDD
VDD
VDD
VDD
VDD
-Vtn
VDD-;Vtn
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MOS devicesSlide 34CMOS VLSI Design
Effective $esistance
Shoc9ley #odels hae li#ited alue $ "ot accurate enou%h for #odern transistors
$ Too co#plicated for #uch hand analysis
Si#plification? treat transistor as resistor
$ Replace Ids&Vds, V%s' with effectie resistance R
J Ids ( Vds)R
$ R aera%ed across switchin% of di%ital %ate
Too inaccurate to predict current at any %ien ti#e $ 2ut %ood enou%h to predict RC delay
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MOS devicesSlide 35CMOS VLSI Design
$C Delay Model
se eKuialent circuits for MOS transistors $ Ideal switch / capacitance and O" resistance
$ nit nMOS has resistance R, capacitance C
$ nit pMOS has resistance ;R, capacitance C Capacitance proportional to width Resistance inersely proportional to width
9%
s
d
%
s
d
9C9C
9C
R)9
9%
s
d
%
s
d
9C
9C
9C
;R)9
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MOS devicesSlide 36CMOS VLSI Design
$C Values
Capacitance $ C ( C% ( Cs ( Cd ( ; f5)µ# of %ate width
$ Values si#ilar across #any processes
Resistance $ R ≈ A LΩµ# in 14Au# process
$ I#proes with shorter channel len%ths nit transistors
$ May refer to #ini#u# contacted deice &F); λ' $ Or #ay.e @ µ# wide deice
$ Doesnt #atter as lon% as you are consistent
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MOS devicesSlide 37CMOS VLSI Design
Inverter Delay Estimate
>sti#ate the delay of a fanout-of-@ inerter
;
@ !
N ;
@
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MOS devicesSlide 38CMOS VLSI Design
Inverter Delay Estimate
>sti#ate the delay of a fanout-of-@ inerter
C
CR
;C
;C
R
;
@ !
N
C
;C
N;
@
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MOS devicesSlide 39CMOS VLSI Design
Inverter Delay Estimate
>sti#ate the delay of a fanout-of-@ inerter
C
CR
;C
;C
R
;
@ !
N
C
;C
C
;C
C
;C
RN
;
@
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MOS d iSlid 40CMOS VLSI D i
Inverter Delay Estimate
>sti#ate the delay of a fanout-of-@ inerter
C
CR
;C
;C
R
;
@ !
N
C
;C
C
;C
C
;C
RN
;
@
d ( ARC