Lec 10 Decoder

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CS1026 1 DECODERS DECODERS A binary code of n bits is capable of representing up to 2^n A binary code of n bits is capable of representing up to 2^n distinct elements of coded information. distinct elements of coded information. A decoder is a combinational circuit that converts binary A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique information from n input lines to a maximum of 2^n unique output lines. output lines. If the n-bit coded information has unused combinations, the If the n-bit coded information has unused combinations, the decoder may have fewer than 2^n outputs. decoder may have fewer than 2^n outputs.

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  • CS1026 1

    DECODERSDECODERS

    A binary code of n bits is capable of representing up to 2^n A binary code of n bits is capable of representing up to 2^n distinct elements of coded information. distinct elements of coded information.

    A decoder is a combinational circuit that converts binary A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2^n unique information from n input lines to a maximum of 2^n unique output lines. output lines.

    If the n-bit coded information has unused combinations, the If the n-bit coded information has unused combinations, the decoder may have fewer than 2^n outputs.decoder may have fewer than 2^n outputs.

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    In digital circuits, one-hot refers to a group of bits among which the In digital circuits, one-hot refers to a group of bits among which the legal combinations of values are only those with a single high '1' bit legal combinations of values are only those with a single high '1' bit and all the others low '0'. and all the others low '0'.

    A similar implementation in which all bits are '1' except one '0' is A similar implementation in which all bits are '1' except one '0' is sometimes called one-cold.sometimes called one-cold.

    A simple decoder circuit is a binary to one-hot or one-cold converterA simple decoder circuit is a binary to one-hot or one-cold converter

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    Three-to-eight-line decoderThree-to-eight-line decoder

    The decoder is a The decoder is a commonly used type of commonly used type of integrated circuit. integrated circuit. This decoder generates all ofThis decoder generates all ofthe minterms of the three input the minterms of the three input variables. variables.

    Exactly one of the output Exactly one of the output lines will be 1 for each lines will be 1 for each combination of the values combination of the values of the input variables.of the input variables.

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    For a boolean function of n variables {x1, ..... xn}, a product term For a boolean function of n variables {x1, ..... xn}, a product term in which each of the n variables appears once (in either its in which each of the n variables appears once (in either its complemented or uncomplemented form) is called a minterm. complemented or uncomplemented form) is called a minterm.

    Thus, a minterm is a logical expression of n variables that employs only Thus, a minterm is a logical expression of n variables that employs only the complement operator and the conjunction operator.the complement operator and the conjunction operator.

    For example, abc, ab'c and abc' are 3 examples of the 8 minterms for a For example, abc, ab'c and abc' are 3 examples of the 8 minterms for a boolean function of the three variables a, b, and c. boolean function of the three variables a, b, and c.

    The customary reading of the last of these is a AND b AND NOT-c.The customary reading of the last of these is a AND b AND NOT-c.

    There are 2^n minterms of n variables, since a variable in the minterm There are 2^n minterms of n variables, since a variable in the minterm expression can be in either its direct or its complemented formtwo expression can be in either its direct or its complemented formtwo choices per n variables.choices per n variables.

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    The term decoder is sometimes also used in conjunction withThe term decoder is sometimes also used in conjunction withother code converters, such as a BCD-to-seven-segment decoderother code converters, such as a BCD-to-seven-segment decoder

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    Some decoders are constructed Some decoders are constructed with NAND gates. Since a NAND with NAND gates. Since a NAND gate produces the AND operation gate produces the AND operation with an inverted output, it with an inverted output, it becomes more economical to becomes more economical to generate the decoder minterms in generate the decoder minterms in their complemented form.their complemented form. Furthermore, decoders include Furthermore, decoders include one or more enable inputs to one or more enable inputs to control the circuit operation.control the circuit operation.

    Two-to-four-line decoder with enable inputTwo-to-four-line decoder with enable input

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    The decoder above can function as a one-to-four-line demultiplexer The decoder above can function as a one-to-four-line demultiplexer when E is taken as a data input line and A and B are taken as the when E is taken as a data input line and A and B are taken as the selection inputs. selection inputs.

    The single input variable E has a path to all four outputs, but the The single input variable E has a path to all four outputs, but the input information is directed to only one of the output lines, as input information is directed to only one of the output lines, as specified by the binary combination of the two selectionspecified by the binary combination of the two selectionlines A and B. lines A and B.

    This feature can be verified from the truth table of the circuit. ForThis feature can be verified from the truth table of the circuit. Forexample, if the selection lines A B = 1 0, output D2 will be the same example, if the selection lines A B = 1 0, output D2 will be the same as the input value E, while all other outputs are maintained at 1. as the input value E, while all other outputs are maintained at 1.

    Because decoder and demultiplexer operations are obtained from Because decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a the same circuit, a decoder with an enable input is referred to as a decoderdemultiplexer.decoderdemultiplexer.

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    The "bobble" (o) present at the The "bobble" (o) present at the end of the NOT gate symbol end of the NOT gate symbol above denotes a signal above denotes a signal inversion (complimentation) inversion (complimentation) of the output signal. But this of the output signal. But this bubble can also be present at bubble can also be present at the gates input to indicate an the gates input to indicate an active-LOW input. active-LOW input.

    This inversion of the input signal is not restricted to the NOT gate only This inversion of the input signal is not restricted to the NOT gate only but can be used on any digital circuit or gate as shown with the operation but can be used on any digital circuit or gate as shown with the operation of inversion being exactly the same whether on the input or output of inversion being exactly the same whether on the input or output terminal. The easiest way is to think of the bobble as simply an inverter.terminal. The easiest way is to think of the bobble as simply an inverter.

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    The prefix SN indicates that The prefix SN indicates that the chip was made by Texas the chip was made by Texas InstrumentsInstruments

    Low-power Schottky TTL (LS) Low-power Schottky TTL (LS) used the higher resistance values used the higher resistance values of low-power TTL and the Schottky of low-power TTL and the Schottky diodes to provide a good diodes to provide a good combination of speed (9.5ns) and combination of speed (9.5ns) and reduced power consumption reduced power consumption (2 mW).(2 mW).

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    A decoder with enable input can function as a demultiplexera A decoder with enable input can function as a demultiplexera circuit that receives information from a single line and directs it to circuit that receives information from a single line and directs it to one of 2^n possible output lines. one of 2^n possible output lines.

    The selection of a specific output is controlled by the bit The selection of a specific output is controlled by the bit combination of n selection lines.combination of n selection lines.

    DecoderDemultiplexerDecoderDemultiplexer

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    The 74139 contains two demultiplexers; pins 1-7 on the left The 74139 contains two demultiplexers; pins 1-7 on the left control the 1st demux, while pins 9-15 control the 2nd demuxcontrol the 1st demux, while pins 9-15 control the 2nd demux

    The schematic symbol for a demultiplexer is an isosceles trapezoid with The schematic symbol for a demultiplexer is an isosceles trapezoid with the longer parallel side containing the output pins and the short parallel the longer parallel side containing the output pins and the short parallel side containing the input pinside containing the input pin

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    This register file makes it possible to simultaneously read from This register file makes it possible to simultaneously read from two registers and write into one register.two registers and write into one register.

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    4 * 16 decoder constructed with two 3 * 8 decoders4 * 16 decoder constructed with two 3 * 8 decoders

    Decoders with enable inputs can be Decoders with enable inputs can be connected together to form a larger connected together to form a larger Decoder circuit. Decoder circuit.

    This shows two 3-to-8-line decoders with This shows two 3-to-8-line decoders with enable inputs connected to form a enable inputs connected to form a 4-to-16-line decoder. 4-to-16-line decoder.

    When w = 0, the top decoder is enabled and When w = 0, the top decoder is enabled and the other is disabled. the other is disabled.

    The bottom decoder outputs are all 0s, and The bottom decoder outputs are all 0s, and the top eight outputs generate mintermsthe top eight outputs generate minterms0000 to 0111. 0000 to 0111.

    When w = 1, the enable conditions are reversed: The bottom decoder outputs generate minterms When w = 1, the enable conditions are reversed: The bottom decoder outputs generate minterms 1000 to 1111, while the outputs of the top decoder are all 0s.1000 to 1111, while the outputs of the top decoder are all 0s.

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    In general, enable inputs are a convenient feature forIn general, enable inputs are a convenient feature forinterconnecting two or more standard components for the interconnecting two or more standard components for the purpose of combining them into a similar function with more purpose of combining them into a similar function with more inputs and outputs.inputs and outputs.

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    A decoder provides the 2^n minterms of n input variables. A decoder provides the 2^n minterms of n input variables.

    Each asserted output of the decoder is associated with a unique Each asserted output of the decoder is associated with a unique pattern of input bits. pattern of input bits.

    Since any Boolean function can be expressed in sum-of-minterms Since any Boolean function can be expressed in sum-of-minterms form, a decoder that generates the minterms of the function, form, a decoder that generates the minterms of the function, together with an external OR gate that forms their logical sum, together with an external OR gate that forms their logical sum, provides a hardware implementation of the function. provides a hardware implementation of the function.

    In this way, any combinational circuit with n inputs and m outputs In this way, any combinational circuit with n inputs and m outputs can be implemented with an n-to-2^n-line decoder and m ORcan be implemented with an n-to-2^n-line decoder and m ORgates.gates.

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    Implementation of a full adder with a decoderImplementation of a full adder with a decoder

    A function with a long list of minterms requires an OR gate with a large number ofA function with a long list of minterms requires an OR gate with a large number ofinputs. A function having a list of k minterms can be expressed in its complemented inputs. A function having a list of k minterms can be expressed in its complemented Form F' with 2^n - k minterms. If the number of minterms in the function is greater than Form F' with 2^n - k minterms. If the number of minterms in the function is greater than 2^n/2, then F' can be expressed with fewer minterms (use NOR gate).2^n/2, then F' can be expressed with fewer minterms (use NOR gate).

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    If NAND gates are used for the decoder, as in then the If NAND gates are used for the decoder, as in then the external gates must be NAND gates instead of OR gates. external gates must be NAND gates instead of OR gates.

    This is because a two-level NAND gate circuit implements This is because a two-level NAND gate circuit implements a sum-of-minterms function and is equivalent to a two-level a sum-of-minterms function and is equivalent to a two-level ANDOR circuit.ANDOR circuit.

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    By means of a DeMorgan Transformation, weve taken our original By means of a DeMorgan Transformation, weve taken our original circuit comprising two ANDs and an OR (with 18 transistors) and circuit comprising two ANDs and an OR (with 18 transistors) and transformed it into a new version comprising three NANDs (with transformed it into a new version comprising three NANDs (with 14). This equates to around a 20% reduction in transistors.14). This equates to around a 20% reduction in transistors.

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    ENCODERSENCODERS

    An encoder is a digital circuit that performs the inverse operation An encoder is a digital circuit that performs the inverse operation of a decoder. of a decoder.

    An encoder has 2^n (or fewer) input lines and n output lines. An encoder has 2^n (or fewer) input lines and n output lines.

    The output lines, as an aggregate, generate the binary code The output lines, as an aggregate, generate the binary code corresponding to the input value. corresponding to the input value.

    An example of an encoder is the octal-to-binary encoder whose An example of an encoder is the octal-to-binary encoder whose truth table is given.truth table is given.

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    Truth Table of an Octal-to-Binary EncoderTruth Table of an Octal-to-Binary Encoder

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    A common application is in A common application is in magnetic positional control magnetic positional control as used on ships navigation or as used on ships navigation or for robotic arm positioning etc. for robotic arm positioning etc.

    Here for example, the angular Here for example, the angular or rotary position of a compass or rotary position of a compass is converted into a digital code is converted into a digital code by a 74LS148 8-to-3 line by a 74LS148 8-to-3 line priority encoder and inputed to priority encoder and inputed to the systems computer to the systems computer to provide navigational data provide navigational data

    8 position to 3-bit output 8 position to 3-bit output compass encoder compass encoder

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    The encoder can be implemented with OR gates whose inputs The encoder can be implemented with OR gates whose inputs are determined directly from the truth table. are determined directly from the truth table.

    Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, or 7. digits 4, 5, 6, or 7.

    These conditions can be expressed by the following Boolean These conditions can be expressed by the following Boolean output functions:output functions:z = D1 + D3 + D5 + D7z = D1 + D3 + D5 + D7y = D2 + D3 + D6 + D7y = D2 + D3 + D6 + D7x = D4 + D5 + D6 + D7x = D4 + D5 + D6 + D7

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    The encoder has the limitation that only one input can be activeThe encoder has the limitation that only one input can be activeat any given time. at any given time.

    If two inputs are active simultaneously, the output produces an If two inputs are active simultaneously, the output produces an undefined combination. undefined combination.

    For example, if D3 and D6 are 1 simultaneously, the output of theFor example, if D3 and D6 are 1 simultaneously, the output of theencoder will be 111 because all three outputs are equal to 1. encoder will be 111 because all three outputs are equal to 1.

    The output 111 does not represent either binary 3 or binary 6. The output 111 does not represent either binary 3 or binary 6.

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    To resolve this ambiguity, encoder circuits must establish an input To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one input is encoded. priority to ensure that only one input is encoded.

    If we establish a higher priority for inputs with higher subscript If we establish a higher priority for inputs with higher subscript numbers, and if both D3 and D6 are 1 at the same time, the output numbers, and if both D3 and D6 are 1 at the same time, the output will be 110 because D6 has higher priority than D3.will be 110 because D6 has higher priority than D3.

    Another ambiguity in the octal-to-binary encoder is that an output Another ambiguity in the octal-to-binary encoder is that an output with all 0s is generated when all the inputs are 0; but this output is with all 0s is generated when all the inputs are 0; but this output is the same as when D0 is equal to 1.the same as when D0 is equal to 1.

    The discrepancy can be resolved by providing one more output to The discrepancy can be resolved by providing one more output to indicate whether at least one input is equal to 1.indicate whether at least one input is equal to 1.

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    Priority EncoderPriority Encoder

    A priority encoder is an encoder circuit that includes the priority A priority encoder is an encoder circuit that includes the priority function. function.

    The operation of the priority encoder is such that if two or more The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the inputs are equal to 1 at the same time, the input having the highest priority will take precedence. highest priority will take precedence.

    They are often used to control interrupt requests by acting on the They are often used to control interrupt requests by acting on the highest priority request.highest priority request.

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    In addition to the two outputs x and y, In addition to the two outputs x and y, the circuit has a third output designated the circuit has a third output designated by V; this is a valid bit indicator that is by V; this is a valid bit indicator that is set to 1 when one or more inputs are set to 1 when one or more inputs are equal to 1. If all inputs are 0, there is no equal to 1. If all inputs are 0, there is no valid input and V is equal to 0.valid input and V is equal to 0.

    The other two outputs are not inspected The other two outputs are not inspected when V equals 0 and are specified as dont-care conditions. Note that whereas Xs in when V equals 0 and are specified as dont-care conditions. Note that whereas Xs in output columns represent dont-care conditions, the Xs in the input columns are useful output columns represent dont-care conditions, the Xs in the input columns are useful for representing a truth table in condensed form.for representing a truth table in condensed form.

    Instead of listing all 16 minterms of four variables, the truth table uses an X to representInstead of listing all 16 minterms of four variables, the truth table uses an X to representeither 1 or 0. For example, X100 represents the two minterms 0100 and 1100either 1 or 0. For example, X100 represents the two minterms 0100 and 1100

    The truth table of a four-input priority encoder.The truth table of a four-input priority encoder.

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    Maps for a priority encoderMaps for a priority encoder

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    Four-input priority encoderFour-input priority encoder

    The condition for output V is an OR function of all the input variables.The condition for output V is an OR function of all the input variables.

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    74148 8-line to 3-line priority encoder74148 8-line to 3-line priority encoder

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    Since inverting the input of Since inverting the input of the YES gate has the same the YES gate has the same effect as inverting the output, effect as inverting the output, an inverting buffer symbol an inverting buffer symbol could also be drawn ascould also be drawn as

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    Active-LOW input, active-LOW output hexadecimal Active-LOW input, active-LOW output hexadecimal (16-line-to-4-line) priority encoder using GS (group select).(16-line-to-4-line) priority encoder using GS (group select).

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    Active-LOW input, Active-LOW input, active-LOW output active-LOW output hexadecimal hexadecimal (16-line-to-4-line) priority (16-line-to-4-line) priority encoderencoder

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    DeMorgan Transformations of AND, OR, NAND, and NOR DeMorgan Transformations of AND, OR, NAND, and NOR functions.functions.

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    Active-LOW input, Active-LOW input, active-LOW output active-LOW output hexadecimal hexadecimal (16-line-to-4-line) (16-line-to-4-line) priority encoderpriority encoder

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