A novel six-band hysteresis control of the packed U cells seven-level converter

Youssef OUNEJJAR (IEEE member), Kamal AL-HADDAD (IEEE Fellow Member)

ÉCOL E D E T ECHNOLOG I E SUP ÉRIEURE

Canada Research chair in Electric Energy Conversion and Power Electronics Département de génie électrique,

1100, rue Notre-Dame Ouest, Montréal (Québec) H3C 1K3 E-mail : ounejjar@ieee.org

E-mail : Kamal.Al-Haddad@etsmtl.ca Abstract- In this paper, authors propose a novel six-band hysteresis technique to control the seven level packed U cells (PUC) converter which was first introduced in [1]. This converter combines advantages of the flying capacitor and the cascaded H-bridge topologies. The study of the novel converter allows the establishment of the switches gates signals equations. In case of rectifier operation, the proposed six-band controller is designed to draw a sinusoidal line current (load current in case of inverter operation) with a unity power factor. Harmonics contents of line current (or load current) and rectifier input voltage (or inverter output voltage) are then very reduced which permits the reduction of the rating of active and passive filters resulting on a very high energetic efficiency and a reduced installation cost. The proposed concept was verified by simulations performed in the Matlab Simulink and SimPowerSystem environments. Index terms: packed U cells, multilevel converters, unity power factor operation, hysteresis

I. INTRODUCTION

Traditional multilevel converters like neutral point converters NPC proposed by Nabae, Takahashi and Akagi [2] and flying capacitors converters FCC proposed by Meynard and Foch [3] present many drawbacks if the number of voltage levels grows. In fact, the number of switches, diodes and capacitors grows excessively resulting on an expensive cost and their implementation becomes very complicated. When number of desired voltage level exceeds three, cascaded H-bridge inverters topology [4] becomes the optimal solution. This is due to their small number of switches and passive components. However, this topology requires independent and isolated DC voltage sources, which leads to the use of transformers.

In the last few years, many optimizations have been presented to improve the efficiency of these multilevel converters [5-11]. In these papers, authors propose multilevel inverters synthesizing a large number of levels with improved output waveforms characterized by a low distortion and smaller filter size. The packed U cells converter combines advantages of flying capacitors converter and cascaded H-bridges one. It uses small number of switches, diodes and capacitors [12-14]. Both pulse width modulation and hysteresis current techniques are used to control multilevel converters. The second strategy has very simple implementation but it presents a sporadic switching frequency, whereas the first strategy has a complex implementation but is characterized by a constant switching frequency. The hysteresis control technique has proven to be the most suitable solution for all the applications of current controlled voltage source inverters where performance requirements are more demanding, such as active filters, drives and high-performance ac power conditioners, albeit at the expense of variable switching frequency. However, some approaches are available in the literature to obtain fixed switching frequency under hysteresis control [15]. In this paper, a novel six-band hysteresis technique is proposed to control the PUC seven level converter in both rectifier and inverter operation. The proposed technique allows a nearly sinusoidal line or load current with a seven level voltage input or output voltage in case of rectifier or inverter operation respectively.

II. PRESENTATION OF THE PACKED U CELLS TOPOLOGY

A topological optimization of the classic cascaded H-bridge inverters results on a new competitive topology which use small number of passive and active components and avoid the use of transformers (figure1.a). A comparison of the PUC topology toward other seven level converters is given in table1. The seven levels neutral point converter NPC and the flying capacitors converter FCC use

978-1-4244-6392-3/10/$26.00 ©2010 IEEE 3199

a very high number of switches, diodes, and capacitors, whereas the hybrid cascaded H-bridge inverters topology use only eight switches. The PUC topology, however, uses only six switches (see figure 1.b).

III. SIX BAND HYSTERESIS CONTROLLER OF THE TRANSFORMERLESS SEVEN LEVEL PUC INVERTER

In figure 1.a, the AC load voltage reference can be generated by the following equation:

dtikikV LiLpan ∫+= ~~11 (1)

Where: LLL iii −= *~, *

Li is the load current reference The capacitor voltage is controlled using a PI regulator such that:

dtvkvki ipL ∫+= ~~22

*

(2) Where: 2

*2

~ vvv −= , *2v is the capacitor voltage reference

In order to generate seven levels output voltage, one must

control the capacitor voltage set point equal to 31V

.

(a)

(b)

Fig.1. Seven level packed U cells (PUC) a- transformerless inverter

b- rectifier

Table1. Comparison of seven level topologies toward PUC converter

Diode clamped

Flying capacitors

Classic cascaded H-bridge

Hybrid cascaded H-bridge

PUC topology

Capacitors 6 6 3 2 2 Clamping

diodes 10 0 0 0 0

Switches 12 12 12 8 6 Table 2: Switching table of the 7-level PUC converter

Van T1 T2 T3 V1 1 0 0

V1-V2 1 0 1 V2 1 1 0 0 0 0 0

-V2 0 0 1 V2-V1 0 1 0

-V1 0 1 1

Thus, the seven level voltages are therefore obtained as given in table 2. iT and iT′ switches operate complementarily, thus, only Ti switches are used. When actual load current is lower that its reference, then, the application of a positive voltage across the load allows their rapprochement Thus, the positive voltages (sector I in figure 2) are applied when the current error Δi, which is the difference between actual load current and its reference, is negative. Contrariwise, the negative voltages (sector II) are applied when the current error is positive. The seven states and their transition conditions are depicted in figure 3.

IV. SIMULATION RESULTS

Simulation was performed in Matlab Simulink and SimPowerSystems environment. The system parameters are the following: Auxiliary DC bus capacitor 4 000 µF Load inductance 10 mH Load resistor 15 Ω Principal DC link voltage V1 300V Hysteresis band 0.2 The auxiliary DC bus (V2 in figure 1.a) is controlled to the third value of the principal one, which is maintained at 300V. The AC load is constituted by a resistor (15Ω) and an inductor (10mH). The auxiliary DC bus voltage V2 is well controlled and remains, in steady state, around the third of the principal DC bus V1. Load current is perfectly sinusoidal as shown in figure 5. Its total harmonics distortion THD is about 0.86%

3200

which is very small (see figure 6.a). A loop effect on the harmonics contents of load current is given in figure 6.b. The load voltage, which is the inverter output voltage, is constituted from seven voltage levels (300, 200, 100, 0, -100, -200, -300) as shown in figure 7.

Fig.2. Six band hysteresis controller of the 7-level PUC

inverter

Fig.3. Chart flow of the six band hysteresis controller

0 0.5 1 1.5 2 2.5 3 3.5 4-20

0

20

40

60

80

100

120

Simulation time (s)

Aux

iliar

y D

C li

nk v

olta

ge (V

)

Fig.4. Evolution of the auxiliary DC bus voltage

2 2.005 2.01 2.015 2.02 2.025 2.03 2.035 2.04 2.045 2.05-15

-10

-5

0

5

10

15

Simulation time (s)

Load

cur

rent

(A)

Fig.5. Load current

(a)

(b)

Fig. 6. Harmonics contents of load current (a) with a loop effect (b)

2 2.005 2.01 2.015 2.02 2.025 2.03 2.035 2.04 2.045 2.05-400

-300

-200

-100

0

100

200

300

400

Simulation time (s)

Inve

rter o

utpu

t vol

tage

(V)

Fig.7. Inverter output voltage

3201

V. NOVEL SIX BAND HYSTERESIS CONTROLLER OF THE SEVEN LEVEL PUC RECTIFIER

Applying the Kirchhoff voltage law to the input of the 7-level PUC rectifier shown in figure 1.b leads to the following equation:

s

anes

Lvv

dtdi −

= (3)

In each state of the 7-level PUC rectifier, the voltage van is constant as shown in table 2. Thus, when the source voltage

and van are positives then dtdis is positive and the line

current increases. Contrariwise, it decreases. When van is positive the capacitors will be in charge or discharge mode if the source voltage is positive or negative respectively. The capacitors are not in charge or discharge mode when van is null. In this case, the line current will increase or decrease if the source voltage is positive or negative respectively. Assuming a unity power factor operation, one can observe that switch T1 is ON only when the current error Δi is negative and the source voltage ve is positive. Thus, the T1 switch pulse can be given by:

( ))sgn(1).sgn(1 ivT e Δ−= (4) Where:

ss iii −=Δ * , is is the line current and is* is its reference

⎩⎨⎧

<≥

=0001

)sgn(x if x if

x i vx e Δ= ,

The analysis of the ON/OFF states of T2 and T3 switches leads to the subdivision of current error into four regions designated by Hi, 4,3,2,1∈i . These regions can be defined by the following equations:

⎩⎨⎧ ≤Δ<

=else 0

0i2.h- if H

11 (5)

⎩⎨⎧

<Δ≥Δ

=2.hi if 02.hi if

H1

2 (6)

⎩⎨⎧ ≤Δ<−≤Δ<

=else 0

0ih- or hi3.h- if H

.213 (7)

⎩⎨⎧ Δ<≤Δ<

=else

i3.h or hih if H

0.21

4 (8)

Where h is the hysteresis bandwidth. The gates pulses of switches T1 and T2 are given by:

⎩⎨⎧

−+=−+=

433

212

)).sgn(1().sgn()).sgn(1().sgn(

HvHvTHvHvT

ee

ee (9)

The amplitude of line current reference is given by:

( ) ( ) ⎟⎠⎞

⎜⎝⎛ +−+⎟

⎠⎞

⎜⎝⎛ +−=

sK

KVVs

KKVVA i

prefi

pref2

2221

111 (10)

Fig.8. Proposed six band hysteresis control technique for 7-level packed U cells rectifier

The line current reference is then generated by multiplying A and the unit vector to ensure a unity power factor operation as shown in figure 8.

VI. SIMULATION RESULTS

The system parameters are the following: Principal and auxiliary DC buses capacitors 4 000 µF Line inductance 3 mH Load resistor 40 ~ 80 Ω Supply network voltage (ve) 120V rms Hysteresis band 0.4 The reference of the principal DC link bus is 250V, thus the reference of the auxiliary DC bus is the third of this value. Figure 9 shows that these voltages are well controlled even under sudden load change (at t=8s). A loop effect of principal DC bus voltage and line current is depicted in figure 10. Figure 13 shows line current before and after load change. Line current is nearly sinusoidal and changes from 9.58A peak to 19.02A peak. The total harmonics distortion THD of line current is about 2.97% which can be lower with a smaller hysteresis band (see figure 12.a). A loop effect on the harmonics contents of line current is given in figure 12.b. Figure 12.c shows the harmonics contents of the line current after load change.

0 2 4 6 8 10 12 14 160

83,3333

166,6666

250

Simulation time (s)

DC

-link

bus

and

aux

iliar

y D

C o

utpu

t vo

ltage

s (V

)

Fig.9. Rectifier output voltages

3202

7.8 7.9 8 8.1 8.2 8.3 8.4 8.5240

245

250

255

260

DC

-link

bus

vol

tage

(V

)

7.8 7.9 8 8.1 8.2 8.3 8.4 8.5

-20

0

20

Simulation time (s)

Line

cur

rent

(A

)

(a)

4 6 8 10 12 14 1674

76

78

80

82

84

86

Simulation time (s)

Auxiliary DC bus (V)

(b)

Fig.10. Loop effect of (a) principal DC link voltage and line current

(b) auxiliary DC bus

4 4.005 4.01 4.015 4.02 4.025 4.03-15

-10

-5

0

5

10

15

Simulation time (s)

Line

cur

rent

(A)

(a)

12 12.005 12.01 12.015 12.02 12.025 12.03-30

-20

-10

0

10

20

30

Simulation time (s)

Line

cur

rent

(A)

(b)

Fig.11. Line current before (a) and after (b) load change

(a)

(b)

(c)

Fig. 12. Harmonics contents of line current before load change (a) with a loop effect (b)

(c) after load change

4 4.005 4.01 4.015 4.02 4.025 4.03-200

-150

-100

-50

0

50

100

150

200

Simulation time (s)

Sou

rce

volta

ge a

nd c

urre

nt (V

, A

)

(a)

3203

12 12.005 12.01 12.015 12.02 12.025 12.03-200

-150

-100

-50

0

50

100

150

200

Simulation time (s)

Sou

rce

volta

ge a

nd c

urre

nt (V

, A

)

(b)

Fig.13. Source voltage and line current before (a) and after load change (b)

4 4.005 4.01 4.015 4.02 4.025 4.03

-250

-166,6667

-83,3334

-0,0001

83,3332

166,6665

250

Simulation time (s)

Rec

tifie

r in

put

volta

ge (

V)

Fig.14. Rectifier input voltage

The switching frequency is sporadic, which is the main characteristic of any hysteresis controller. However, it can be limited at low frequencies by acting on the hysteresis band. The unity power factor operation is maintained even under load variation as shown in figure 13. The rectifier input voltage is constituted from seven level voltages (250, 166.67, 83.33, 0, -83.33, -166.67, -250) as shown in figure 14. The simulation results show a good dynamics of the proposed system.

VII. CONCLUSION

A novel six band hysteresis control technique for the seven level packed U cells converter is presented in this paper. The proposed controller allows a nearly sinusoidal current both in rectifier or inverter operation. The DC link buses voltages are well controlled and track their references even under load steps. The rectifier input voltage or the inverter output voltage has seven level voltages which permits to reduce the rating of active and passive filters resulting on a very high energetic efficiency and a reduced installation

cost. The good dynamics of the system prove the efficiency of the proposed controller.

REFERENCES

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