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CXXXX American Chemical Society

Dual-GatedMoS2/WSe2 van derWaalsTunnel Diodes and TransistorsTania Roy,†,‡,§,0 Mahmut Tosun,†,‡,§,0 Xi Cao, ),0 Hui Fang,†,‡,§ Der-Hsien Lien,†,‡,§,^ Peida Zhao,†,‡,§

Yu-Ze Chen,# Yu-Lun Chueh,# Jing Guo, ) and Ali Javey*,†,‡,§

†Electrical Engineering and Computer Sciences, University of California, Berkeley, California 94720, United States, ‡Materials Sciences Division, Lawrence BerkeleyNational Laboratory, Berkeley, California 94720, United States, §Berkeley Sensor and Actuator Center, University of California, Berkeley, California 94720,United States, )Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida, United States, ^Department of Electrical Engineering,National Taiwan University, Taipei, Taiwan, and #Materials Science and Engineering, National Tsing Hua University, Hsinchu, Taiwan. 0T. Roy, M. Tosun, and X. Caocontributed equally.

Scaling of the metal-oxide-semiconduc-tor field-effect transistors (MOSFETs) inthe IC industry for over 5 decades and

16 technology nodes has been driven inparallel with the reduction of the operatingvoltage to balance out the power dissipa-tion and consumption of the electronicsystems. The inadequate scaling of operat-ing voltage, VDD, with increasingly diminish-ing technology node, however, has led topower consumption issues recently as theMOSFETs approach their minimal VDD,which is governed by their switching mech-anism. Specifically, the carrier injection inMOSFETs is based on thermionic emission

over the energy barrier at the source, whichtheoretically limits the MOSFETs' subthresh-old swing to SS ≈ 60 mV/dec at roomtemperature and places a floor for thresholdvoltage scaling as well. In order to maintaina minimum ION/IOFF of ∼106, the supplyvoltage is thus limited to about 6 � 60 mV,corresponding to VDD≈ 360mV in the mostoptimistic case. In reality, SS for state-of-the-art MOSFETs is larger than the theoreticallimit, and furthermore, to obtain sufficientlyhigh ON-state currents for fast switchingoperations, a higher VDD needs to be ap-plied. This supply voltage limitation ofMOSFETs represents an important challenge

* Address correspondence toajavey@eecs.berkeley.edu.

Received for review December 19, 2014and accepted January 18, 2015.

Published online10.1021/nn507278b

ABSTRACT

Two-dimensional layered semiconductors present a promising material platform for band-to-band-tunneling devices given their homogeneous band edge

steepness due to their atomically flat thickness. Here, we experimentally demonstrate interlayer band-to-band tunneling in vertical MoS2/WSe2 van der

Waals (vdW) heterostructures using a dual-gate device architecture. The electric potential and carrier concentration of MoS2 and WSe2 layers are

independently controlled by the two symmetric gates. The same device can be gate modulated to behave as either an Esaki diode with negative differential

resistance, a backward diode with large reverse bias tunneling current, or a forward rectifying diode with low reverse bias current. Notably, a high gate

coupling efficiency of∼80% is obtained for tuning the interlayer band alignments, arising from weak electrostatic screening by the atomically thin layers.

This work presents an advance in the fundamental understanding of the interlayer coupling and electron tunneling in semiconductor vdW heterostructures

with important implications toward the design of atomically thin tunnel transistors.

KEYWORDS: transition metal dichalcogenide . electron tunneling . negative differential resistance . TFET . steep . 2D

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facing the IC industry given the continued increase intransistor density. Therefore, exploring new switchingmechanisms is of fundamental interest for futureenergy-efficient electronics. One promising alternativeswitch to aMOSFET is a tunneling field-effect transistor(TFET), where carrier injection is governed by band-to-band tunneling (BTBT) of electrons, which doesnot depend on thermal processes.1 Thus, in principle,SS < 60 mV/dec should be achievable with TFETs. Todate, significant progress has beenmade in exploring awide range of TFET device architectures using carbonnanotubes2 and Si,3 Si�Ge,4 and III�V semicon-ductors.5�7 Both homojunction and heterojunctiondevice configurations have been explored, with theheterojunction devices exhibiting higher ON-state cur-rent densities due to the ability to obtain sufficientlysmall (or even zero) tunneling barrier heights by usingmaterials with proper band alignments.8 Despite tre-mendous advancements in the field, to date a TFETwith SS < 60mV/dec overmultiple current decades andhigh ON-state current densities has not been demon-strated experimentally. Various studies have shownthat the band edge roughness of the explored semi-conductors in combination with the trap states at thesurface and heterojunction interfaces are limiting theswitching steepness of the experimental devices.9

Specifically, imperfections at the tunneling interfacedue to lattice mismatch and spatial inhomogeneity inthickness and composition can reduce the sharpnessof the band edges. In addition, doping is known tofurther reduce band edge sharpness given the randomdistribution of the dopant atoms in the lattice. Toovercome these fundamental limitations, explorationof new material systems is required. For instance,transition metal dichalcogenides (TMDCs), a family oftwo-dimensional layered materials, show promise to-ward obtaining steep band edge tunneling devices,since they intrinsically exert atomic level flatness dueto their layered crystal structure.10,11 The ability to stackone two-dimensional material onto another can createan atomically sharp interface, without any unwantedatomic diffusion or dislocation propagation due tolattice mismatch.12 The absence of dangling bondsand a surface native oxide (for the TMDCs investigatedin this work)13�15 allows for the formation of ultrathinvertical heterostructures with minimal trap states.Sharpness of the band edges in MoS2 and WSe2monolayers as well as MoS2/WSe2 heterobilayers hasbeen previously reported by using photoluminescencemeasurements. A nearly identical inverse slope of30 mV/dec was reported from the analysis of the bandtails of monolayers and heterobilayers, signifying thatsharp band edges can be experimentally obtained invan der Waals (vdW) heterostructures.13 Given thismeasured optical band edge sharpness, it is feasibleto envision that tunnelingdeviceswith SS≈ 30mV/decshould be, in principle, possible when using vdW

heterostructures. However, before the realization oftunnel transistors using TMDC heterostructures, band-to-band tunneling and its fundamental properties inthese vdW materials need to be explored.Electronic and optoelectronic properties of vdW

heterostructures, based on graphene, h-BN, andTMDCs have been studied extensively in the recentpast. For instance, graphene�insulator�grapheneheterostructures have exhibited interlayer tunnelingwith negative differential resistance (NDR).16,17 Whiledemonstrating the feasibility of vertical tunneling ofelectrons in vdW heterostructures, graphene-basedtunnel devices cannot be effectively turned off dueto the lack of an intrinsic band gap. In the past year,significant research has been carried out on MoS2/WSe2 heterostructures.13,18�21 Artificially stacked ex-foliated monolayer MoS2/WSe2 heterostructures exhi-bit a Stokes-like shift in the photoluminescence peakand the lowest absorption peak, suggestive of a spa-tially direct absorption and spatially indirect emissionin a type II band alignment with strong interlayerelectronic coupling.13,21 These heterostructures exhibitrectifying diode behavior, with rectification of 4 ordersof magnitude in the forward bias current, which can begate controlled.13,21 However, a detailed study toinvestigate vertical BTBT in TMDC-based heterojunc-tions has not been reported, and it is yet unknown as towhether an efficient BTBT current density can beobtained in TMDC vdW devices. In theory, by electro-statically tuning the band alignment from type II totype III (broken gap), vertical tunneling of electronsfrom the valence band of one layer to the conductionband of another can be initiated.22 Tunneling junctionsand the realization of a Zener diode, whose reversebias breakdown is caused by BTBT, are the first stepstoward eventual fabrication of a TFET. In addition totheir use as the building block of TFETs, Zener diodesare commonly used in analog circuits due to their highnonlinearity. Thus, exploration and characterizationof Zener diodes based on TMDC heterostructures isof tremendous scientific and technological interest.In this work, dual-gated MoS2/WSe2 heterostructure

tunnel diodes and transistors are examined experi-mentally and theoretically. The electrostatic potentialand carrier concentration of MoS2 and WSe2 layers areindependently controlled by two separate gate elec-trodes. Symmetric dual-gate device architecture isessential, compared to single-gate or asymmetricdual-gate structures, in order to effectively controlthe band alignment at the vertical heterojunction byindependently modulating the electric potential inboth top and bottom layers. In the case of single-gateor asymmetric dual-gate structures, the electric fieldfrom one gate dominates the potential of both layers,resulting in poor controllability of the heterojunction.Selective electron and hole contacts are made to MoS2and WSe2 layers, respectively. By using this device

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structure, Zener tunneling is observed in the reversebias, when the two gates are biased at oppositepolarities such that the MoS2 and WSe2 layers are instrong electron and hole accumulationmodes, respec-tively. Under such a circumstance, the device resem-bles an nþ/pþ diode with a large built-in potential,Vbi, operating as a backward diode. Some of thedevices also exhibit negative differential resistancein the forward bias, indicative of Esaki diode characterand a broken gap (type III) band offset.When the samedevice is subjected to lower gate fields, the bandoffset at the heterojunction is changed to a staggeredgap (type II), resulting in lower reverse bias tunnelingcurrents and higher forward bias diffusion current dueto reduced Vbi. Thus, the same device is shown tobehave in various diode regimes, merely by tuningthe gate voltage, a phenomenon unseen in covalentlybonded semiconductor material systems. This con-trollability of the diode operation regime was ob-served in six fabricated devices, with nearly identicalthickness of MoS2 and WSe2 components ranging

from 2 to 8 layers. In conventional semiconductordevices, the same device cannot behave as bothforward rectifying and backward/tunnel diodes, sincethey require different chemical doping conditions.Another fundamental difference in the material prop-erties of vdW heterostructures compared to con-ventional semiconductor heterostructures is in thebonding at the tunneling interface. Heterostructuresof III�V compounds and Si�Ge have covalent bond-ing at the interface that pins the band offsets at thetunneling interface, irrespective of the doping leveland the applied voltage, unless an insulator layer isgrown in between the layers. In contrast, in the vdWheterostructures, potential can be dropped across thevdW gap, thus allowing the bands of the two materialcomponents to freely move with respect to eachother at the junction by the applied drain voltage orelectrostatic doping by the two gates. Therefore, vdWheterostructures provide a new degree of freedom interms of modulation of the band offsets at the tunnel-ing interface.

Figure 1. Device structure. (a) Optical microscope images and (b) corresponding schematics (not to scale) for the fabricationprocess steps of a representative dual-gatedMoS2/WSe2 diode. (i) Local bottom gate electrodewith Ni as themetal electrodeand ZrO2 as the gate dielectric. (ii) MoS2 and WSe2 layers dry-transferred onto the bottom gate and etched to form arectangular heterostructure. (iii) Metal contacts to MoS2 (Ni) and WSe2 (Pd) deposited, as source and drain electrodes,respectively. (iv) Top-gate stack with ZrO2 as the gate dielectric and Ni metal as the electrode. Scale bar = 10 μm in all opticalimages. (c). Three-dimensional schematic of the device (not to scale). (d) Cross-sectional TEM image of a representative deviceshowing the symmetric dual-gate structure. (e) High-resolution STEM image of the same heterostructure, consisting of4 layers of MoS2 and WSe2. (f) EDS mapping of the heterostructure.

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Figure 1 shows the fabrication process and cor-responding optical images of a dual-gated MoS2/WSe2 tunnel diode. A local back gate was fabricated(see Methods), as shown in Figures 1a(i) and b(i). MoS2flakes were mechanically exfoliated onto a Si/SiO2

carrier chip. The carrier chip was spin coated withPMMA. The MoS2 flake of interest was dry-transferredonto the targeted local back gate using a previouslyreported pick and transfer process.23 The sample wasannealed at 180 �C for 2min to ensure proper adhesionof the flake to the substrate. The PMMA layer wasremoved by using dichloromethane, leaving the flakeattached to the local back gate. A WSe2 flake wastransferred on top of the MoS2 layer using the sametransfermethod.WSe2was aligned overMoS2 in such away as to avoid overlap in the edge regions, in order toallow for selective electrical contacts to each layer. Theheterojunction (i.e., overlap region) is therefore only inthe middle of the flake. The rectangular heterostruc-ture shape was defined via electron beam lithographyand etched using XeF2 gas.

24 This shape formation isimportant for eliminating unwanted current pathssuch as those from nonoverlapping MoS2/WSe2 re-gions along the width of the device (Figure 1a(ii) andb(ii)). Ni electrodes were patterned as electron contactsto MoS2. Special attention is drawn to the fact thatNi does not contact WSe2 or the heterostructure. Pdelectrodes were then patterned to act as hole contactsto WSe2. The fabricated structure with the contacts isshown in Figure 1a(iii) and b(iii). A top gate stack wasthen patterned on the heterostructure area. The deviceis designed such that the bottomand top gates overlapthe heterostructure area in the middle of the device.The bottom gate also overlaps the electron contact tothe MoS2 layer, while the top gate overlaps the holecontact to WSe2 in order to minimize the parasiticresistances in the device. Figure 1a(iv) shows theoptical image of a representative dual-gate MoS2/WSe2 device. The heterostructure area is defined bythe overlapped region of the bottomand the top gates,as shown in the schematic of Figure 1b(iv). Figure 1cshows the corresponding three-dimensional schematicof the complete device. A cross-sectional transmission

electron microscope (TEM) image of a representativedevice is shown in Figure 1d, clearly depicting thesymmetric dual-gate structure. The high-resolutionscanning TEM (STEM) image of the MoS2/WSe2 hetero-structure (Figure 1e) shows a sharp and clean inter-face between MoS2 and WSe2, with each materialbeing ∼4 atomic layers in thickness. Figure 1f showsthe energy-dispersive X-ray spectroscopy (EDS)mapping of the heterostructure. The top 4 layers arecomposed of W and Se, while the bottom layers arecomposed of Mo and S. Figure S1 shows the Ramanspectra from the MoS2/WSe2 heterostructure in a dual-gated device.

RESULTS AND DISCUSSION

The fabricated devices were electrically character-ized at different temperatures and under differentdrain and gate voltages. Figure 2a shows the operationof a dual-gated MoS2/WSe2 heterostructure diode at77 K. The MoS2/WSe2 heterostructure for this deviceconsists of 8�10 layers ofMoS2 and 6�8 layers ofWSe2as measured by atomic force microscopy (AFM). TheMoS2/WSe2 heterostructure area is 2.8 μm

2. The ID�VDof the diode is shown as a function of varying WSe2gate voltage, VGate‑WSe2, while keeping the MoS2 gatevoltage, VGate‑MoS2, constant at 3 V (Figure 2a). AtVGate‑MoS2 = 3 V, the MoS2 layer is electrostaticallyrendered highly n-type, due to strong accumulationof electrons. When VGate‑WSe2 = �2 V, the WSe2 layercan be assumed to be in a condition of weak accumu-lation of holes. The device resembles an nþ/p diodewith a staggered gap band offset. Under this condition,the diode demonstrates the expected rectification inthe forward bias due to diffusion current, with lowreverse bias current limited by the noise floor of themeasurement setup. A forward to reverse currentrectification of 7 orders of magnitude is observed.When VGate‑WSe2 is decreased to�2.5 V, the WSe2 layeris further accumulated with holes. In this situation, Vbiof the diode increases, resulting in lower forward biascurrent for the same drain voltage conditions as in theprevious case. A significant reverse bias current arisesat VD < �0.5 V and is due to Zener tunneling of

Figure 2. Gate tunability of a representative dual-gated device at 77 K. MoS2 is 8�10 layers in thickness, and WSe2 is 6�8layers thick as confirmed fromAFMmeasurements. (a) ID�VDwith varyingVGate‑WSe2;VGate‑MoS2 = 3 V. (b) ID�VDwithVGate‑WSe2

varied with 0.1 V increments from �2 V to �0.9 V; VGate‑MoS2 = 2 V. (c) Tunneling onset voltage vs VGate‑WSe2, with the sloperepresenting the gate coupling efficiency η.

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electrons in the valence band of WSe2 to the conduc-tion band of MoS2. Upon further decrease of VGate‑WSe2

to �3 V, the accumulation of holes in WSe2 increasesfurther. In this case, the device resembles an nþ/pþdiode, and the forward bias current diminishes belowthe noise floor of the measurement setup, due toincreased Vbi, for the same drain voltage range (1 V)used in the previous two cases. The reverse bias currentis increased and is 4 orders of magnitude larger thanthe forward current, which is at the noise level. Thedevice behaves like a backward diode, where thereverse bias current due to Zener tunneling is largerthan the forward bias current for the applied drainvoltage range of�0.75 to 1 V. Thus, we demonstrate afour-terminal diode whose operation regimes arehighly controllable by its dual gates, without theapplication of any physical dopant. Similar tunabilityof operation regimes of a MoS2 (bilayer)/WSe2 (bilayer)device is shown in Figure S2.It is important to understand the efficiency of gate

control inmoving the band edges of MoS2 andWSe2 atthe heterointerface. In order to elucidate the gatecontrol electrostatics on the device behavior,Figure 2b shows the tunability of the same device atVGate‑WSe2 varying from�0.9 to�2 Vwith an incrementof 100 mV at 77 K. VGate‑MoS2 is kept at a constantvoltage of 2 V, resulting in the accumulation of elec-trons in MoS2. The device exhibits Zener tunneling(marked “BTBT” in Figure 2b) in the reverse bias, andthe tunneling onset voltage shifts to more negative VDas VGate‑WSe2 is made less negative. Simultaneously, theminority carrier drift current, often referred to asthe reverse bias saturation current, I0, increases asVGate‑WSe2 is made less negative. This behavior isexpected since the minority (majority) carrier concen-tration in WSe2 is decreased (increased) as higher gatefields are applied to WSe2. The device operates like aclassical diode when the chemical doping concentra-tions of the two components are changed. Here, more-over, the same device can be readily modulated toexhibit different carrier concentrations by tuning thetwo gate voltages. Figure 2c shows the reverse biastunnel onset voltage (i.e., tunneling breakdownvoltage), Vtunnel, as a function of VGate‑WSe2. Vtunnel isdefined as the voltage at which a tunnel current of10�11 A is measured. The slope of Vtunnel vs VGate‑WSe2

gives the gate coupling factor or the gate efficiency η(Figure 2c). It signifies that for each volt applied to thegate, the Fermi level can be moved by 0.84 V. This highgate efficiency arises from the use of high-k gatedielectrics and thin MoS2 and WSe2 layers. We observesaturation in the reverse bias tunneling current and theforward bias current due to the large parasitic resis-tance of the contacts, especially for WSe2, since thecontact regions were not doped.25�27 This large para-sitic resistance also lowers the steepness of the BTBTcurrent in our fabricated diodes. In the future, doping

of contacts needs to be explored for lower parasiticresistances.A phenomenological device model is developed to

further understand the gate-bias-dependent diodecharacteristics (Figure 3). Electrostatic potential foreach TMDC layer is obtained by solving the carrierstatistics equations self-consistently with the Poissonequation in the form of a capacitance model, which isdescribed in a previous work on vertical tunnelingtransistors.28 Then, two mechanisms are taken intoaccount in source�drain current calculation for inter-layer carrier transport. The first one is an elastic processat the interface, including the direct tunneling andthermionic emission, which is shown as path I inFigure 3b. The current generated by this process canbe described by16

Je ¼ Rqp

ZDMoS2 (E � qVMoS2 )DWSe2 (E � qVWSe2 )

�[fWSe2 (E) � fMoS2 (E)] dE (1)

whereDMX2 is the density of state (DOS) for each TMDCand fMX2 is the source/drain Fermi level. VMoS2 andVWSe2 are electrostatic potentials of theMoS2 andWSe2layer, which account for both gate and drain bias andcan be solved self-consistently as described before. p isthe reduced Planck's constant, q is electron charge, andR is a fitting parameter that is related to the elastictransport time as τ1 = p/(RDMX2). For simplicity, theDOS in the conduction or valence band is assumed tobe constant, which is similar to previous studies ontunneling devices.14 The band tail states whose DOSexponentially decay as a function of the differencebetween the energy E and the band edge energy areincluded in the band gap.Besides this elastic process, there is also an inelastic

interlayer carrier recombination process. Differentfrom a conventional PN junction, the atomically thinjunction does not have any depletion region in thevertical direction. Thus, the majority of holes in WSe2are in direct contact with the majority of electronsin MoS2, separated by only a vdW gap. As a result,the interlayer majority carrier recombination is pro-nounced.13,21 This inelastic process can be eitherphoton or phonon assisted. We refer to this inelasticprocess as current path II, as illustrated in the schematicof Figure 3b. Simply, we adapted a second transporttime of the carrier, τ2, which is the interlayer recombi-nation lifetime, to account for the inelastic process, sothat the current can be estimated by

Jine ¼ qnp � n0p0τ2(nþ p)

(2)

where n and p are the electron and hole density ofadjacent MoS2 and WSe2 layers, and n0 and p0 areelectron and hole density at equilibrium conditions.As described in a previous study,21 eq 2 assumes the

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Shockley Read Hall (SRH) mechanism for interlayermajority carrier recombination, and an assumption ofthe Langevin mechanism results in a different quanti-tative equation but does not change the qualitativeconclusions. Finally, the total current conducted by thePN junction is the addition of these two processes, J =Je þ Jine. Figure 3a and c show the simulated ID�VDcharacteristics of a bilayer/bilayer diode under twodifferent gate voltage conditions, with τ2/τ1 = 1. Athigh gate overdrive voltages (Figure 3a), both theMoS2and WSe2 layers remain accumulated even when amoderate reverse bias is applied. As a result, Zenertunneling takes place through band edge states or theband tail states in the band gap region very close to theband edge. The reverse bias current is contributed byZener tunneling and is nonsaturating. In comparison,at a lower top gate overdrive voltage (Figure 3c),the WSe2 layer becomes depleted as a reverse bias isapplied. The depletion leads to a saturated reversebias current. The results indicate that the operationmodes of the diode can be modulated by the appliedgate voltage, qualitatively consistent with the experi-ment. The quantitative difference can be attributedto us ignoring the parasitic resistance and noise in

simulations and the uncertainty of the material anddevice parameters. The following parameters wereused in the simualtions: in Figure 3a, n0 = 1.01 �1013 m�3, p0 = 2.91 � 1011 m�3, while in Figure 3c,n0 = 3.15 � 1014 m�3, with n0 . p0. Figure S3a,b showthe simulated band diagrams for a MoS2 (bilayer)/WSe2(bilayer) device, indicating the influence of the gate oneach layer.We measured the diode characteristics as a function

of temperature in order to further analyze the dual-gated MoS2/WSe2 heterostructure (Figure 4). Here,the device consists of a MoS2/WSe2 stack with eachmaterial being 2 layers in thickness. The MoS2/WSe2overlap area is 18 μm2. To obtain backward diode char-acteristics, the devicewas biasedwith VGate‑MoS2 = 3.5 Vand VGate‑WSe2 = �4 V, and the correspondingID�VD characteristics are shown in Figure 4a. Thetunnel current onset voltage shifts positively withincreasing temperature, which is a characteristic ofthe Zener tunneling processing due to the change inthe band gap (and band tail states) with temperature.The tunnel current onset voltage, Vtunnel, is defined asthe voltage with the reverse bias tunnel current of10�13 A. The slope of Vtunnel vs T is the temperature

Figure 3. (a) Simulated ID�VD characteristics of a MoS2/WSe2 (2 layers each) diode at VGate‑MoS2 = 3 V and VGate‑WSe2 = �3 V, at77 K. (b) Corresponding qualitative band diagrams at forward and reverse biases. (c) Simulated ID�VD characteristics of the diodeat VGate‑MoS2 = 3 V and VGate‑WSe2 = �2 V, at 77 K. (d) Corresponding qualitative band diagrams at forward and reverse biases.

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coefficient of tunneling breakdown, θ, in the MoS2/WSe2 materials system, which is measured to be�4.8 mV/K (Figure 4b). This temperature coefficient issimilar in value to a typical Si Zener diode, which has areported coefficient of �2 to �3 mV/�C.29 The tem-perature dependence of the forward rectifying char-acteristics, corresponding to lower applied gate fields,of the same device is shown in Figure 4c. The built-inpotential, Vbi, decreases with increasing temperature,and the slope of the forward bias current decreasesslightly with temperature. The reverse bias current forthis diode configuration increases with temperatureas the recombination�generation current increases.Figure 4d shows the inverse slope, in mV/dec, of thetunnel current for the backward diode configurationand the forward current for the forward-rectifying diodeconfiguration as a function of inverse temperature. Theinverse slope of the tunnel current remains nearlyconstant with temperature, as expected for Zener tun-neling. The inverse slope of the forward current de-creases slightly with inverse temperature. This is incontrast to a covalently bonded p�n junction, wherethe forward bias current is dominated by diffusion ofmajority carriers with its inverse slope changing linearlywith T. The lack of strong temperature dependence inthe forward bias current suggests that an inelasticcurrent mechanism (path II in Figure 3b) dominatesthe forward bias current over the diffusion current. Thisis consistent with previous photoluminescence studies,where themain exciton recombinationwas shown tobespatially indirect arising from the recombination ofelectrons in MoS2 with holes in WSe2.

13,21

The carrier transport time, τ2, described earlier forthis inelastic process can vary across samples, due tothe quality of the interface during device fabrication. Ifτ2 is long compared to τ1, the elastic tunneling (i.e.,BTBT) process can dominate over the inelastic recom-bination process in the forward bias. Figure 5 showsthe electrical characteristics of another dual-gatedMoS2/WSe2 device. The stack consists of 4 MoS2 layersand 4 WSe2 layers, with an overlap area of 4.6 μm2.When VGate‑MoS2 = 3 V and VGate‑WSe2 =�3 V, the deviceexhibits negative differential resistance in the forwardbias, as shown in Figure 5a, thus behaving like an Esakidiode. Both the NDR peak position and peak-to-valleyratio are controlled by the applied gate voltages. AsVGate‑WSe2 is made more negative, the NDR peak posi-tion shifts to higher positive voltage and the peak-to-valley ratio increases. The peak of the NDR signifies theposition when the conduction band edge of MoS2 isaligned with the valence band edge of WSe2. Byvarying VGate‑WSe2, the drain bias at which the MoS2conduction band edge and WSe2 valence band edgeare aligned is varied. Thus, the voltage position of thepeak of the NDR as a function of VGate‑WSe2 is anindicator of the gate coupling efficiency. A gate cou-pling efficiency of∼80% is obtained (Figure 5b), whichis consistent with the previous devices. It is worthnoting that no correlation of observation of NDR withthe flake thicknesses (for the explored thickness rangeof up to 10 layers) was observed in our experiments. Adetailed investigation of device characteristics as afunction of flake thicknesses and the correspondingband structures should be carried out in the future.

Figure 4. (a) Temperature dependence of the tunnel current at VGate‑MoS2 = 3.5 V and VGate‑WSe2 =�4 V of a device. MoS2 andWSe2 are 2 layers each in thickness for this device. (b) Tunneling onset voltage vs temperature at VGate‑MoS2 = 3.5 V andVGate‑WSe2 = �4 V. (c) Temperature dependence of the forward diode current at VGate‑MoS2 = 3.5 V and VGate‑WSe2 = �2 V.(d) Inverse slopes of the BTBT current (VGate‑MoS2 = 3.5 V and VGate‑WSe2 =�4 V) and forward bias current (VGate‑MoS2 = 3.5 V andVGate‑WSe2 = �2 V) vs inverse temperature.

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Figure 5c shows the temperature dependence of theNDR at VGate‑MoS2 = 3 V and VGate‑WSe2 =�3 V. The NDRdiminishes after 175 K due to thermionic currentsuppressing the tunneling current in the forward bias.Figure 5d shows the simulated ID�VD characteristicsat different temperatures, under a bias condition ofVGate‑MoS2 = 3 V and VGate‑WSe2 = �3 V. A lifetime ratioof τ2/τ1 = 100 is assumed. The results show clear NDRbehaviors at low temperature. At a low forward biasnear equilibrium, an elastic carrier transport path, corre-sponding to BTBT, contributes to the current. As theapplied forward bias increases, the elastic carrier trans-port path is closed with the overlap of the band edgesdiminishing, leading to an NDR characteristic. Similar toexperiments, NDR is only observed at low temperatures.The simulated NDR is much more pronounced com-pared to the experimental ID�VD, even by considering anonideal band edge with a decaying band gap state of30 meV/decade.13 To explain the lower peak-to-valueratio observed in the experiment, we further examinethe role of the inelastic transport denoted as path II inFigure 3b. Decrease of the interlayer recombinationtime results in a more efficient path II, as shown inFigure 5e and increase of the valley current. As shown inFigure 5f, the simulated peak-to-valley current ratio issensitive to the ratio of the carrier transport times of theinelastic interlayer transport process, τ2, and the elastic

interlayer carrier transport process, τ1. A low peak-to-valley ratio of the NDR characteristics in the experimen-tal device is, therefore, due to efficient interlayer major-ity carrier recombination.

CONCLUSION

In conclusion, we have demonstrated band-to-bandtunneling current in vertical MoS2/WSe2 heterostruc-tures by using a symmetric dual-gate device architec-ture. The same device can be operated as an Esakidiode, a backward diode, or a forward rectifying diodeby tuning the applied gate voltages, making the devicehighly versatile. Notably, a high gate coupling effi-ciency of ∼80% is demonstrated for tuning the bandoffsets at the MoS2/WSe2 vertical interface. Theoreticalsimulations confirm that the diode operation modescan be easily modulated by the two gates due to weakelectrostatic screening by the 2D layers. Both experi-ments and theory depict the importance of inelasticcurrent transports in vdW vertical heterostructures inthe forward bias operation mode, arising from lack of acharge depletion region along the vertical direction.The demonstration of 2D-to-2D tunneling is an impor-tant finding in semiconducting layered materials. Thiswork establishes the possibility of using vdW semicon-ductor heterostructures in tunnel transistors for futurelow-power electronics.

METHODS

Device Fabrication. The bottom gate was fabricated usingelectron-beam lithography, with 50 nm Ni contact thermally

evaporated, followed by 20 nm ZrO2 deposited by atomic layerdeposition at 110 �C. MoS2/WSe2 flakes were patterned next. Ni(50 nm) was thermally evaporated as contact to MoS2, and50 nm of Pdwas e-beam evaporated as contact toWSe2. For the

Figure 5. (a) ID�VD at VGate‑MoS2 = 3 V and VGate‑WSe2 varied. MoS2 and WSe2 are 4 layers each in thickness for this device.Negative differential resistance is observed at forward bias. (b) Voltage at which NDR peak occurs vs VGate‑WSe2. (c)Temperature dependence of the NDR at VGate‑MoS2 = �VGate‑WSe2 = 3 V. (d) Simulated temperature dependence of NDR atVGate‑MoS2 = �VGate‑WSe2 = 3 V, by assuming a lifetime ratio of τ2/τ1 = 100. (e) Qualitative band diagrams corresponding topoints I (NDR peak) and II (NDR valley) in (d). (f) SimulatedNDRpeak-to-valley current ratio (PVCR) vs inelastic to elastic carriertransport time ratio (τ2/τ1).

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top gate stack, SiOx (∼1 nm) was evaporated as nucleation layerfor atomic layer deposition of ZrO2 (20 nm) deposited at 110 �Cas the gate dielectric. Ni (50 nm) was then evaporated as the topgate contact.

Electrical Measurements. The MoS2/WSe2 heterostructuredevices were electrically characterized under vacuum in aLakeshore cryo-probe station. Devices were measured usingan Agilent B1500A semiconductor parameter analyzer.

Conflict of Interest: The authors declare no competingfinancial interest.

Supporting Information Available: Raman spectrum of aMoS2/WSe2 heterostructure; simulated band diagrams; andadditional experimental device data. This material is availablefree of charge via the Internet at http://pubs.acs.org.

Acknowledgment. The device fabrication and characteriza-tion was funded by the Center for Low Energy Systems Tech-nology (LEAST), one of six centers supported by the STARnetphase of the Focus Center Research Program (FCRP), a Semi-conductor Research Corporation program sponsored byMARCO and DARPA. The material processing, including thedry-transfer steps for the heterostacks, was funded by theDirector, Office of Science, Office of Basic Energy Sciences,Material Sciences and Engineering Division of the U.S. Depart-ment of Energy, under Contract No. DE-AC02-05CH11231. H.F.and P.Z. were funded by NSF E3S.

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Dual-Gated MoS2/WSe2 van der Waals Tunnel

Diodes and Transistors

Tania Roy1,2,3*, Mahmut Tosun1,2,3*, Xi Cao4*, Hui Fang1,2,3, Der-Hsien Lien1,2,3,5, Peida

Zhao1,2,3, Yu-Ze Chen6, Yu-Lun Chueh6, Jing Guo4, and Ali Javey1,2,3,†

1Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, 94720.

2Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, CA 94720.

3Berkeley Sensor and Actuator Center, University of California, Berkeley, CA, 94720.

4Department of Electrical and Computer Engineering, University of Florida, FL

5Department of Electrical Engineering, National Taiwan University, Taiwan

6Materials Science and Engineering, National Tsing Hua University, Taiwan

* Equally contributing authors

† Corresponding Author: ajavey@eecs.berkeley.edu

Supporting Information

S2

Raman spectroscopy of MoS2/WSe2 heterostructures

Figure S1 shows the Raman spectrum of a MoS2/WSe2 heterostructure in a dual-gated

device. The MoS2 and WSe2 in this device are each two layers thick. The optical image of the

device is shown in Fig S1a. The Raman spectrum (Fig. S1b) was taken at the red mark on the

heterostructure (Fig. S1a), using a depolarized laser with the wavelength of 532 nm. The

spectrum was collected and averaged over 10 exposures, each of 10 s duration. The spot size of

the laser was 1 µm in diameter (Gaussian). In Fig S1b, the characteristics Raman peaks of WSe2

and MoS2 can be distinctly observed. WSe2 shows the E2g peak at 251 cm-1. The E2g peak of

MoS2 is observed at 384 cm-1 and the A1g peak occurs at 407 cm-1.

Figure S1. (a) Optical image of a dual-gated MoS2/WSe2 heterostructure device. Scale bar =

10 µm. (b) Raman spectrum of the MoS2/WSe2 heterostructure taken at the point marked in

(a) with a red circle.

S3

Gate tunability of diode operation in MoS2 (bilayer)/ WSe2 (bilayer) device

Figure S2 shows the backward diode to forward rectifying operation regimes of a dual-gated

MoS2/WSe2 heterojunction device at 77 K, with MoS2 and WSe2 each being 2 layers thick.

-1.0 -0.5 0.0 0.5 1.010

-15

10-13

10-11

10-9

10-7

10-5

I D (

A)

VD (V)

VGate-WSe2

= -2 V

VGate-WSe2

= -3.5 V

VGate-WSe2

= -4 V

VMoS2-Gate

= 3.5 V

Tunneling

Diffusion

Figure S2. Tunability of diode operation regimes of a MoS2 (2L)/ WSe2 (2L) device.

S4

Simulated band diagrams for a MoS2 (2L)/ WSe2 (2L) device

In the simulation, the density of states (DOS) in the conduction or valence band is assumed to be

constant, and the band tail states whose DOS exponentially decay as a function of the difference

between the energy E and the band edge energy are included in the bandgap. The bandgap values

used are 1.46eV and 1.445eV for bilayer MoS2 and bilayer WSe2, respectively.1

Figure S3a-b show the band diagrams from the device model shown in main text for a MoS2

(bilayer)/ WSe2 (bilayer) heterostack device. The influence of gate on each layer of the

heterojunction is clearly manifested.

Figure S3. Simulated band diagrams for MoS2 (2L)/ WSe2 (2L) device at (a) VGate-WSe2 =

-3 V, VGate-MoS2 = 3 V, and (b) VGate-WSe2 = -2 V, VGate-MoS2 = 3 V.

S5

Simulated band diagrams for MoS2 (2L)/ WSe2 (2L) device under conditions for resonant

tunneling

Figure S4 shows the band diagrams of a simulated MoS2/WSe2 device with each being two

atomic layers thick. The lifetime ratios of carriers are chosen such that resonant tunneling is

observed at forward bias.

Figure S4. Simulated band diagram of MoS2 (2L)/WSe2 (2L) under conditions for resonant

tunneling. Bias I and II are the same as shown in Fig. 5d of main text.

S6

References:

1. Yun, W. S.; Han, S. W.; Hong, S. C.; Kim, I. G.; Lee, J. D. Thickness and strain effects

on electronic structures of transition metal dichalcogenides: 2H-M X-2 semiconductors (M =

Mo, W; X = S, Se, Te). Physical Review B 2012, 85.