Aix History

7/30/2019 Aix History

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7 Y E A R S O F I B M R I S C

1965

1974

19851986

19901992

19931994

1995 19961997

19981999

2000 2001 2002 2003 2004

America

POWER

RSC

POWER2

P2SC POWER3

POWER3-II

POWER4

POWER4+

POWER5

IBMACS

the801

PowerPC601

Powe

rPC604

PowerP

C603e,604e

PowerPC970

RTPC

RS64

RS64 IIRS6

4III

RS64 IV

SP SP2 SP2

Overview

AIXV1/2

AIXV3

AIXV3.2.5

AIXV4.1

AIXV4.2

AIXV4.3

AIX 5LV5.0

AIX 5LV5.1

AIX 5LV5.2

AIX 5LV5.3

1965 IBM ACSIn the 1960's IBM was behind in the scientific

area and wanted to design an advancedmachine better than the CDC 6800, later calledthe CDC 7600.The idea for the ACS (IBM Advanced ComputingSystems) design started in 1965 with JohnCocke's vision of a scientific supercomputer.This was several years earlier than the RISCwork at Berkeley and Stanford Universities. The

ACS project (which evolved from "Project Y",that started late 1963) was cancelled in 1968.Many of the innovative CPU organizationtechniques pioneered in ACS were used in theIBM RS/6000.

After ACS, John Cocke carried thisunderstanding of compilers and instruction setswith him to the IBM 801 project. John alsogreatly influenced the IBM Cheetah and Americaprojects, which were the predecessors to theRS/6000.Links:A Secret 1960's Supercomputer ProjectIBMs ACS-1 MachineTechnical Description of IBM ACS Project

The A.M. Turing Award1987: John Cocke for significantcontributions in the design andtheory of compilers, thearchitecture of large systems andthe development of reducedinstruction set computers (RISC);for discovering and systematizingmany fundamentaltransformations now used inoptimizing compilers includingreduction of operator strength,elimination of commonsubexpressions, registerallocation, constant propagation,and dead code elimination.

1974the 801IBM Reduced Instruction Set Computer (RISC) technology originated in 1974 in a project at theThomas J. Watson Research Center to design a large telephone-switching network. The

computer needed was named the 801 (after Building 801, where the research was taking place).The goal of the 801 was to execute one instruction per cycle. The experimental 801 was neverbuild, but the design, mostly developed by IBM researcher John Cocke, seemed to be an goodbasis for a general-purpose, high-performance miniprocessor.Links:The evolution of RISC technology at IBM(PDF)

1985 AmericaBased on the experimental design of the 801 and ACS ideas the development laboratory in

Austin completed a first prototype, where it evolved into the superscalar (Instructions are handled
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paralel) RISC System/6000 (RS/6000) processor that was introduced into the market in 1990.Development work had been done under code name "America" for the RISC chip research, and"RIOS" for systems using the America technology.

1986 RT PCThe IBM RT PC is IBM's first RISC based UNIX (Advanced Interactive Executive [AIX]) computer

with 32 bits ROMP processor (without floating point capability ...) that was first announced by IBMin January 1986. The IBM RT has had a varied life from its initial announcement. The RT wasconsidered as "not enough power, too high a price, and too late" and thought to be part of IBM'sPersonal Computer line ... (hence RT PC, later renamed to RT).Links:6150 RT PC Models 020, 025, and A25 IBM 6151 RT PC model 010FAQ for AIX V2.2.1 on IBM RT systems 1234

1986 Advanced Interactive ExecutiveAIX for the RT PC is announced. The RT used the Virtual Resource Manager (VRM) thatprovided a virtual machine environment for the kernel, allowing more than one operating systemto execute. AIX was based on INTERACTIVE Systems Corporation's IN/ix (the first commercialUnix).Links:

IBM RT Personal Computer System OverviewThe IBM RT PC Advanced Interactive Executive (AIX) Operating SystemRT PC AIX and Virtual Resource ManagerRT PC AIX Version 2.1

1987 AIX (PS/2)IBM will provide the PS/2 AIX Operating System as a subset of the multiuser, multitasking, virtualmemory AIX operating system currently available on the IBM RT PC.Links:PS/2 AIX Statement of DirectionAvailability of PS/2 AIX delayed ...

1990 POWERFebruari 1990 IBM announces its new RISC-based computer line, the RISC

System/6000 (later named RS/6000, nowadays eServer pSeries), running AIXVersion 3. The architecture of the systems is given the name POWER (nowcommonly referred to as POWER1), standing for Performance Optimization WithEnhanced RISC. They where based on a multiple chip implementation of the 32-bitPOWER architecture. The models introduced included an 8 KB instruction cache (I-cache) and either a 32 KB or 64 KB data cache (D-cache). They had a singlefloating-point unit capable of issuing one compound floating-point multiply-add (FMA) operationeach cycle, with a latency of only two cycles and optimized 3-D graphics capabilities.

The model 7013-540 (30 MHz) processed 30 million instructions per second. Its electronic logic

circuitry had up to 800,000 transistors per silicon chip. The maximum memory size was 256

Mbytes and its internal disk storage capacity was 2.5 GBytes.Links:RISC System/6000 POWERstation/POWERserver 320

RISC System/6000 POWERstations/POWERservers 520 AND 530RISC System/6000 POWERserver 540RISC System/6000 POWERstation 730RISC System/6000 POWERserver 930

AIX Version 3AIX Version 3 is announced.Links:AIX Version 3 (Februari, 1990)Overview: IBM RISC System/6000 and related announcements
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1991With the alliance of Apple and Motorola, IBM started a plan for the future that would span a rangefrom the small, battery-operated computer to very large supercomputers and mainframes,resulting in the PowerPC family of microprocessors, a single-chip implementation for RISC-basedhardware and software.Links:Understanding IBM pSeries Performance and Sizing

1992 RSCJanuary of 1992, the model 7011-220 (33 MHz) , an entry-level desktopworkstation, was announced, based on a single chip implementation of thePOWER architecture, usually referred to as RISC Single Chip (RSC). I recallwe used to say "the pizza box".Links:RISC System/6000 POWERstation/POWERserver 220, 22W AND 22G

AIX PS/2 Version 1.3Announcement of AIX PS/2 Operating System Version 1.3 for IBM PS/2.Links:AIX PS/2 Operating System V1.3 (September 1992)Withdrawal: IBM AIX PS/2 Operating System 1.3 (December 1994)

1993 SPThe IBM Scalable POWERparallel Systems (SP, now commonly referred to as SP1) offer ascalable platform for both serial and parallel applications. Based on RISC System/6000technology, the basic component of the in Februari 1993 announced9076 SP1is a system framecontaining eight to 16 RISC System/6000 processor nodes (max. four frames, 64 nodes).The SP implements Massively Parallel Processing (MPP). All the processing nodes have theirown resources (processors, memory, disks and operating system): the shared nothingarchitecture.Links:AIX Parallel EnvironmentSP models 001, 002, 003, 004, A01, AND 101More SP models2001 SP Overview

PowerPC 601The RISC System/6000 model 7011-250 (66 MHz) workstation, the first to be based on the 32-bitPowerPC 601 processor, was introduced in September 1993.The 601 was the first processor arising out of a partnership between IBM, Motorola, and Apple.From IBM, the RISC Single Chip (RSC) microprocessor became the base design for 601. Thesuperscalar machine organization of the 601 was improved to achieve greater performance andadditional custom circuit design was applied to reduce the die size and to allow higher frequencyoperation. The Motorola 88110 microprocessor bus interface formed the basis of thedevelopment of the 601 bus interface.The 601 did not implement the full PowerPC instruction set (some infrequently used instructionwhere excluded) and some new instructions and features were added, such as support for

symmetric multiprocessor (SMP) systems. The 601 is capable of dispatching, executing, andcompleting up to 3 instructions per cycle. Instructions issue to multiple execution units (an integerunit, a branch processing unit, and a floating-point unit), execute in parallel, and can complete outof order.

An SMP has multiple processors that have their own cache, the memory and devices are shared.The 601 was a bridge from POWER to the full PowerPC architecture, such as the 603, 604, and604e.Links:POWERstation/POWERserver 250 Series
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POWER2The model 7013-590 (66 MHz) was announced in September 1993 and was the first RS/6000

based on the 32-bit POWER2 architecture. The most significant improvement introduced with thePOWER2 architecture for scientific and technical applications is that the floating-point unit (FPU)contains two 64-bit execution units, so that two floating-point multiply-add instructions may beexecuted each cycle. A second fixed-point execution unit is also provided. In addition, several

new hardware instructions were introduced with POWER2: quad-word storage instructions,hardware square root instruction and floating-point to integer conversion instructions.Initial models: 7013-58H (55 MHz), 7013-590 (66 MHz), 7015-990 (71.5 MHz).Links:POWER2 and PowerPC architecture

AIX Version 3.2.5AIX V3.2.5 is announced: Maturity (stability, quality).Links:AIX Version 3.2.5(September, 1993)

1994 NotebookThe RS/6000 7007-N40 (50 MHz) notebook workstation (introduced in March) is the idealportable companion for mobile professionals who want to take AIX on the road. Based on the

PowerPC 601.Links:7007-N40 IBM RS/6000 Model N40

SP2

The Scalable POWERparallel Systems 2 (SP2) was announced in April 1994. Based on IBM's

RISC System/6000 microprocessor technology and running AIX/6000 (as it was named then), the

SP2 could scale from two to 128 nodes (processing elements). Using a POWER2 processor and

other options it performed twice the processing power of the SP1 system.Links:Scalable POWERparallel Systems 9076 SP2 and Enhancements for SP1Scalable Parallel Computing9076-xxx SP Family

AIX Version 4.1AIX Version 4.1 is announced: Scalability (PowerPC support, 4-way SMP, Client/Server pkg),new Standards compliance, Simplicity (graphical, fast installation, Common DesktopEnvironment), HACMP Clustering.Links:AIX Version 4.1 (July, 1994)AIX Version 4 Overview and Product Life Cycle DatesAIX Version 4.2 Overview and Product Life Cycle DatesAIX Version 4.3 Overview and Product Life Cycle Dates

1995 PowerPC 60432-bit PowerPC 604RISC System/6000 microprocessor (120 MHz) upgrade announced for theRISC System/6000 model 7020-40P (66 MHz).Links:Motorola/IBM PowerPC 604/604e

Windows NT PowerPC EditionAnnouncement of Windows NT Workstation 3.51 for RS/6000 40P, 43P and with NT 4.0 (1996)other models.Hmmm ... I'm not going to try it on my 43P ...Windows NT Workstation 3.51 Now Supports IBM Power SeriesWindows NT Support for PowerPC Computers
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1996 POWER2 Super ChipOctober 1996 the RS/6000 model 7013-595 (135 MHz) was announced with the new 32-bitPOWER2 Super Chip (also known as P2SC). The P2SC is a single chip implementation of thePOWER2 eight-chip architecture, containing 15 million transistors on a single chip using high-density CMOS-6S technology. It powered the wide and thin nodes in SP systems.Links:SP POWER2 Super Chip Nodes

RS/6000In October (?) IBM renames RISC System/6000: RS/6000.

PowerPC 603eOctober 1996, announcement of the portable workstation RS/6000 model 860(166 MHz) -notebook - using the 32-bit PowerPC 603e processor.

PowerPC 604eThe 43P models 140 and 240 with 32-bitPowerPC 604e RS/6000microprocessor (166 MHz) are announced. The 604e is a superscalar processorcapable of issuing four instructions simultaneously. As many as seveninstructions can finish execution in parallel.Links:PowerPC 604e Technical Library

Windows NT for the PowerPC withdrawn

AIX Version 4.2AIX Version 4.2 is announced: High-end scalability ( 8-way SMP, >2GB memory), Standards:UNIX95 brand, RAS Enhancements, NFS V3.Links:AIX Version 4.2 (April 23)

1997 RS64The RS64 (also known as Apache) is the first 64-bit PowerPC RISC processor (October 1997).The RS64 is a superscalar processor optimized for commercial workloads. The processor hasseparate 64 KB L1 cache for instructions and data and L2 cache controllers. The L2 caches runat full processor speed. The RS64 contains a 16 byte interface to 2-way set associative 4MB L2cache. The RS64 is also used in the AS/400 (called A35). Predecessors of the A35, only runningOS/400 are the A10 (a.k.a. Cobra), the world's first 64-bit PowerPC microprocessor, and A25(a.k.a. Muskie).IBM brings 64-bit technology to the market introducing the RS/6000 Enterprise Server model7017-S70(125 MHz, code named Raven), the first 12-way SMP system, and AIX Version 4.3.Links:RS/6000 Enterprise Server Model S70 Blazes the 64-Bit Trail

AIX Version 4.3AIX Version 4.3 is announced: Higher levels of scalability (24-way SMP, 96 GB memory), 32/64-bit API support, UNIX98 Branding, Networking/Security (TCP/IP V6, IPsec), Web SystemManagement, AIX Workload Manager, Java JDT/JIT, 32-bit/64-bit application coexistence andconcurrent execution (the kernel is still 32 bits).Links:AIX Version 4.3 (October 1997)AIX Version 4.3.1(April 1998)AIX Version 4.3.2(October 1998)
http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=09&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=595&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=09&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=POWER2+Super+Chip&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=860&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=860&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=Z7DoYmPCUifs*l1USenGnN9332&xhi=salesmanual%5E&type=D&search=7043&title=T&product=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=604e&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www-3.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_604e_Microprocessorhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=XsZBRvt5Ch3Ce32USenGnN9332&request=announcements&parms=H_296-124&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=wojto4cDu7ZKxk1USenGnN9332&xhi=salesmanual%5E&type=D&search=&title=T&product=7017-s70http://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=wojto4cDu7ZKxk1USenGnN9332&xhi=salesmanual%5E&type=D&search=&title=T&product=7017-s70http://www2.ibmlink.ibm.com/cgi-bin/master?xh=u98COmS0Jdchxk1USenGnN9332&request=announcements&parms=H_197-265&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=4WTUv90NTHdDxk1USenGnN9332&request=announcements&parms=H_297-399&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=TcWpG1k3b*5Exk1USenGnN9332&request=announcements&parms=H_298-108&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=TcWpG1k3b*5Exk1USenGnN9332&request=announcements&parms=H_298-108&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_298-359&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_298-359&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=09&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=595&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=09&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=POWER2+Super+Chip&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=860&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=Z7DoYmPCUifs*l1USenGnN9332&xhi=salesmanual%5E&type=D&search=7043&title=T&product=http://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1996&emonth=11&eday=31&eyear=1996&searchwords=604e&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www-3.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_604e_Microprocessorhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=XsZBRvt5Ch3Ce32USenGnN9332&request=announcements&parms=H_296-124&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=wojto4cDu7ZKxk1USenGnN9332&xhi=salesmanual%5E&type=D&search=&title=T&product=7017-s70http://www2.ibmlink.ibm.com/cgi-bin/master?xh=u98COmS0Jdchxk1USenGnN9332&request=announcements&parms=H_197-265&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=4WTUv90NTHdDxk1USenGnN9332&request=announcements&parms=H_297-399&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=TcWpG1k3b*5Exk1USenGnN9332&request=announcements&parms=H_298-108&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_298-359&xfr=N


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1998 RS64 IIPowerPC RS64 II 64-bit RISC microprocessor (also know as NorthStar) is the first in the

Star series processor family.The in July 1998 announced RS64-II contains a dedicated 32 byte interface to a private 4-way

set associative 8MB L2 cache. The processor target operating frequency is 262 MHz. The 262MHz cards contain four processors per card. Up to three 4-way cards can be installed in a

RS/6000 7017-S70 to create a 4-way, 8-way, or 12-way system.Links:New Processors Enhance the IBM RS/6000 Model S70 Performance

POWER3The new 64-bit POWER3 processor, announced October 1998, unifies the POWER2 architecture(P2SC) with the PowerPC architecture, and was optimized for technical applications.The SMP-capable POWER3 design allows for concurrent operation of f ixed-point instructions,load/store instructions, branch instructions, and floating-point instructions. The POWER3 iscapable of executing up to four floating-point operations per cycle (two multiply-add instructions).Integer performance has been significantly enhanced over the P2SC with the addition ofdedicated integer and load/store execution units. The chip features eight execution units fed by a6.4 gigabyte-per-second memory subsystem. The core includes two high-bandwidth buses: a128-bit 6XX architecture bus to main memory and 256-bit bus to the L2 cache that runs atprocessor speed. The POWER3 also has on-chip 64KB data cache and a 32KB instructioncache.IBM's first 64-bit symmetric multiprocessor (SMP) workstation is the POWER3 based RS/600043P7043-260 (200 MHz).Links:RS/6000 43P 7043 Model 260The POWER3 MicroarchitectureOverview of Recent SupercomputersHistory of POWER processorsCharacterization of Web Server Workloads on Three Generations of IBM PowerPC Microarchitectures(PDF)

1999 RS64 IIIPowerPC RS64 III 64-bit RISC microprocessor (also known as Pulsar) using copper technology.The RS64 III microprocessor powers the in September 1999 announced RS/6000 model 7017-

S80 (450 MHz). The frequency of 450 MHz was accomplished by using IBM's new coppertechnology (CMOS 7S). The RS64 III has 8 MB of Level 2 (L2) cache per processor. The 6-waySMP can be expanded to a 24-way SMP and the system memory can be expanded to 96 GB.Links:Custom circuit design as a driver of microprocessor performance

AIX Version 4.3.3AIX Version 4.3.3 is announced.links:AIX Version 4.3.x Overview and Product Life Cycle DatesAIX Version 4.3.3 UNIX Operating System( September 1999)

2000 POWER3-IIThe 64-bit POWER3-II microprocessor design is

based on IBM's advanced CMOS 7S process,which is a re-implementation of POWER3 usingcopper interconnects.New RS/6000 model 44P 7044-270(375 MHz)using the 1-4 way SMP with POWER3-II copper-based microprocessor.The POWER3-III didn't surface, so POWER4 isthe next ...Links:Power3-II 375/450 MHz Processors

The use

copper"wiring" forintegratedcircuits in1997 was abreakthroughinsemiconductor technology(smaller,faster, morepowerful and
http://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=Ntpi*BVj*1pdxk1USenGnN9332&xhi=salesmanual%5E&type=D&search=7017&title=T&product=http://www2.ibmlink.ibm.com/cgi-bin/master?xh=u98COmS0Jdchxk1USenGnN9332&request=announcements&parms=H_198-170&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=i70$T7RUqqchvk1USenGnN9332&request=salesmanual&parms=H_7043-260&xhi=salesmanual%5E&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=i70$T7RUqqchvk1USenGnN9332&request=salesmanual&parms=H_7043-260&xhi=salesmanual%5E&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1998&emonth=11&eday=31&eyear=1998&searchwords=260&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www.research.ibm.com/actc/Talks/FrankOConnell/index.htmhttp://www.phys.uu.nl/~steen/web01/overview01.htmlhttp://www.research.ibm.com/actc/RS_6000/Topic_Parallel.htmlhttp://www.research.ibm.com/acas/projects/web_server.pdfhttp://www.research.ibm.com/acas/projects/web_server.pdfhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=hmKb1ajddof2yk1USenGnN9332&request=announcements&parms=H_199-225&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=hmKb1ajddof2yk1USenGnN9332&request=announcements&parms=H_199-225&xfr=Nhttp://www.research.ibm.com/journal/rd/446/allen.htmlhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=Ntpi*BVj*1pdxk1USenGnN9332&request=salesmanual&parms=H_5765-C34&xhi=salesmanual%5E&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_299-255&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_299-255&xfr=Nhttp://www-1.ibm.com/servers/eserver/pseries/hardware/workstations/44p_270.htmlhttp://www-1.ibm.com/servers/eserver/pseries/hardware/workstations/44p_270.htmlhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=AM7cLpeQVeaVwk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1999&emonth=08&eday=28&eyear=2001&searchwords=POWER3-II&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www2.ibmlink.ibm.com/cgi-bin/master?request=salesmanual&parms=SMS&xh=Ntpi*BVj*1pdxk1USenGnN9332&xhi=salesmanual%5E&type=D&search=7017&title=T&product=http://www2.ibmlink.ibm.com/cgi-bin/master?xh=u98COmS0Jdchxk1USenGnN9332&request=announcements&parms=H_198-170&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=i70$T7RUqqchvk1USenGnN9332&request=salesmanual&parms=H_7043-260&xhi=salesmanual%5E&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=rBtEKnlHHBLNsk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1998&emonth=11&eday=31&eyear=1998&searchwords=260&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=http://www.research.ibm.com/actc/Talks/FrankOConnell/index.htmhttp://www.research.ibm.com/actc/Talks/FrankOConnell/index.htmhttp://www.phys.uu.nl/~steen/web01/overview01.htmlhttp://www.research.ibm.com/actc/RS_6000/Topic_Parallel.htmlhttp://www.research.ibm.com/acas/projects/web_server.pdfhttp://www.research.ibm.com/acas/projects/web_server.pdfhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=hmKb1ajddof2yk1USenGnN9332&request=announcements&parms=H_199-225&xfr=Nhttp://www1.ibmlink.ibm.com/cgi-bin/master?xh=hmKb1ajddof2yk1USenGnN9332&request=announcements&parms=H_199-225&xfr=Nhttp://www.research.ibm.com/journal/rd/446/allen.htmlhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=Ntpi*BVj*1pdxk1USenGnN9332&request=salesmanual&parms=H_5765-C34&xhi=salesmanual%5E&xfr=Nhttp://www2.ibmlink.ibm.com/cgi-bin/master?xh=xEMBfgm*16Q2xk1USenGnN9332&request=announcements&parms=H_299-255&xfr=Nhttp://www-1.ibm.com/servers/eserver/pseries/hardware/workstations/44p_270.htmlhttp://www2.ibmlink.ibm.com/cgi-bin/master?request=announcements&parms=S&xh=AM7cLpeQVeaVwk1USenGnN9332&type=ANNO&smonth=00&sday=01&syear=1999&emonth=08&eday=28&eyear=2001&searchwords=POWER3-II&content=TITLE&n$0=&n$1=&n$2=&n$3=&n$4=&n$5=&n$6=&n$7=&n$8=&n$9=


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RS/6000 44P 7044 Model 270Why copper?Back to the Future: Copper Comes of Age less costly).The firstcopper chip

was aPowerPC forApple iMacsystems(September1998).

eServer pSeriesIn October IBM renames RS/6000: eServer pSeries.Links:IBM introduces servers for the next generation of e-businessA Server By Any Other Name

RS64 IVPowerPC RS64 IV 64-bit RISC microprocessor (also known as Sstar) using copper and SOItechnology.The in October 2000 announced pSeries 680(600 MHz) a is 6- to 24-way 64-bit SMP server withup to 96GB of system memory and 16MB L2 cache for each 600 MHz processor.Links:

A multithreaded PowerPC processor for commercial servers

AIX 5L Version 5.0The initial release of AIX 5L was not generally available. It was an Early Adopter Release forOEM's and application developers to begin development of true 64-bit applications for a 64-bit

AIX kernel.

Silicon-on-insulator ( SOI) technology improves performance over bulk CMOS technology by up to35% and reduces power requirements by up to 66%. SOI refers to placing a thin layer of silicon on topof an insulator such as silicon oxide or glass. The transistors would then be built on top of this thinlayer of SOI. The basic idea is that the SOI layer will reduce the capacitance (the ability of a structureto store electrical charge) of the switch, so it will operate faster. SOI protects the millions transistors ona chip with a blanket of insulation, reducing harmful electrical effects that consume energy and hinderperformance. The first SOI/copper-based chip was shipped in May 1999 (a PowerPC processor usedin new AS/400 models).

2001 POWER4The POWER4 "Gigaprocessor"copper SOI 64-bit CMPmicroprocessor is based on all earlier

designs.174-million-transistor POWER4 chip, with two 1.1/1.3GHz five-issue superscalar microprocessor cores, atriple-level cache hierarchy, up to 256 GB memory, a10-Gbyte/s main-memory interface, and a 45-Gbyte/smultiprocessor interface. The POWER4 is a CMPchip, which means that it incorporates multipleprocessors on a single piece of silicon.

AIX 4.3.3 is not supported on Power4.Links:IBM Journal of R & D - Vol. 46, No. 1, 2002 - IBM POWER4 SystempSeries 690 System Handbookp690 -- a collection of white papersp690 puts SPECjbb2000 leadership to restPOWER4 System MicroarchitectureeSever pSeries 690 AnnouncementpSeries 690: Virtual TourIBM POWER4 microprocessor focuses on memory bandwidth (PDF)IBM Project RegattaLogical Partitioning (LPAR)

The in October introduced 8- to 32-way 64bit SMP server7040-681 (type model, whichis not logical ...) pSeries 690(code-namedRegatta H) is the first server to use thePOWER4 dual processor on a chip, and isthe first model in the Regatta family).Advanced MultiChip Module (MCM)packaging places up to eight POWER4processors onto a package that fits in thepalm of a hand (8.5x8.5 cm).

This new class of pSeries is the first UNIX Datacentersystem, utilizing mainframe-inspired self managementcapabilities (eLiza). Integrated static Logical Partitioning(LPAR) support for up to 16 AIX 5L or Linux partitions.
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IBM ResearchVLSI MicroprocessorsLinux and AIX link up on IBM's biggest Unix serverSilicon-on-insulator (SOI)andCopper TechnologyVARBusiness: IBMs p690 Server: Less Is More

AIX 5L Version 5.1

AIX 5L Version 5.1 is announced in April: Higher levels of scalability (POWER4 Support, 32-waySMP, 256GB memory, full 64bit kernel and device drivers, Logical Partitioning), Advanced RAS,Networking enhancements, Java 2 Version1.3, Linux Application Support (Linux affinity). AIX 5.1also supports 32-bit POWER architecture and Intel Itanium (on a limited basis) architecture.Links:AIX 5LAIX 5L Version 5.1Monterey - AIX on Itanium ?Gartner assesses IBM's AIX 5L OS - Source: ZDNet

SP2 OverviewThe RS/6000 SP system hosts dozens to hundreds of RISCprocessor nodes facilitating parallel processing capability.The basic SP building block is the processor node. It consists of a

POWER3 or PowerPC Symmetric Multiprocessors (SMP), memory,Peripheral Component Interconnect (PCI) expansion slots forInput/Output (I/O) and connectivity, and disk devices. Nodes haveeither a Symmetric MultiProcessor (SMP) configuration (using PCI)or a uniprocessor configuration (using MCA). The three types ofnodes (thin, wide, and high) may be mixed in a system and arehoused in short or tall system frames. Depending on the type ofnodes used, an SP tall frame can contain up to 16 nodes and an SPshort frame can contain up to 8 nodes. These frames can beinterconnected to form a system with up to 128 nodes (512 byspecial order). Each node contains its own copy of the AIXoperating system.Links:RS/6000 SP and Clustered IBM eServer pSeries Systems Handbook

RS/6000 SP ProcessorsAdvanced Computer Technology Center (ACTC)RS/6000 SP Resource CenterRS/6000 SP Planning Volume 1, Hardware and Physical Environment

The currentlyused 375 or 450MHz POWER3SMP nodes, are

powered by the64-bit 375 or 450MHz POWER3-IImicroprocessor.Earlier nodesused POWER1(62 MHz),POWER2 (66/77MHz), PowerPC604

(112/200/332 MHz), P2SC(120/135/160 MHz) and POWER3(200/222 MHz).

2002 POWER4+The POWER4+ processors (the name POWER4-II circulated before the announcement) areannounced in November 2002.Source: ComputerWire, 21/01/2002Links:IBM launches world's most powerful eight-way UNIX server and new POWER4+ processor

AIX 5L Version 5.2AIX 5L Version 5.2 is announced in October:

Logical Partitioning (LPAR) Support

Dynamic LPAR adds or removes processors, adapters and memory withoutrequiring areboot

Dynamic reconfigurations APIs permit middleware and applications toautomaticallyadjust to system resource changes

Dynamic Capacity Upgrade on Demand (CUoD) permits activation ofadditionalprocessors without requiring a reboot
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Dynamic Processor Sparing (with CUoD) permits substitution of failedprocessors withspare, unlicensed processors

Scalability, Capacity and Resource Management

16MB Large Pages speed transfer of data from storage to memory onPOWER4enterprise systems

Memory Affinity and Scheduling Affinity localize workloads internally byutilizing a subsetof processors that share uniform access to a subset of systemmemory on POWER4enterprise systems

JFS2 file size and file system support increased to 16TB and adds native filesystemsnapshot support

Enablement added for VERITAS File System Workload Manager module is dynamic for the management of resourceswithin a

partitioned or single-image system. Enhanced to offer time-basedresource policies andautomatic administrator notification when resourcelimits reached on "per class" basis.New resources managed include numberof processes, logins and connect time

Networking Performance and Technology

Adds Mobile IPv6 enabling the connection of hand-held devices to theinternet Network tunable parameters can be persistent and managed through SMIT orthrough

Web-based System Manager Asynchronous Transfer Mode (ATM) is enhanced with the addition of Userto Network

Interface 4.0 (UNI), Integrated Local Management Interface 4.0(ILMI) with increasedframe sizes and dynamic MTU size

Reliability, Availability & Serviceability (RAS)

System UE-Gard detects errors that formerly would result in a checkstop and instead justterminates the affected thread

Adds automatic "lost I/O" detection and recovery Dynamic Processor Deallocation default is set to "enabled" Enhanced diagnostics that identify adapter cards and storage devices byphysical

location Adds graphical trace log viewer Improved dump size estimation and scripting for Automated Dump Analysis Added Multi-path I/O enablement for improved connectivity and maintenancedeferral

Security

Adds Internet Key Exchange (IKE) support for DHCP servers

Adds Diffie-Hellman key agreement protocol Adds full Pluggable Authentication Module (XSSO/PAM) support to helpunify differentlogin mechanisms and reduce administrative overhead

Adds authentication via x.509 certificates Adds IKE use of new, integrated random number generator Kerberized r-commands are added to the security services suite Adds enablement for Enterprise Identity Mapping which is intended to associatethe

identity of a user in one registry with the identity of the same user inanother registry


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System Management

Adds centralized management of groups of AIX servers via DistributedCommandExecution Manager application

Adds capability to manage Linuxoperating system-based Intelserversalong with AIX-based POWER servers

System tuning parameters are centralized in SMIT and the Web-basedSystem Manager Adds Linux client for Web-based System Manager

Interoperability

Base / Standards

UNIX 98 Server certified Adds POSIX Asynchronous I/O support Adds DNS Bind Version 9 support for networking Adds LDAP client support for RFC 2307, IBM Directory and custom schemafor

networking SNMP protocol upgraded to Version 3 Common Host Bus Adapter (HBA) API added to improve storage interoperabilityand

management CIM management objects support added for web-based system management

Tools for Performance, debugging and transition

AIX Toolbox for Linux Applications now includes more than 380applications Adds template-based AIX performance tuning via a stanza based file thatsupports

persistent values and can be exported/imported to multiple servers Adds consolidated access to performance tuning values in SMIT andWeb-based System

Manager Adds xprofiler (GUI-based profiling tool) to the base operating system Adds performance tools support for LPAR, Large Pages and MemoryAffinity Adds new thread analysis tools, curt and splat, to the analysis tool suite Adds performance toolbox and iostat support for ESS vpaths tprof tool is enhanced to provide multiple process profiling, improved threadssupport and

support for emulation and alignment interrupts Kernel debugger is enhanced for crash and lldb functions prtconf is enhanced to display processor speed Adds 14 new commands for /proc and 31 additional SVR4 commands

Links:AIX Documentation Library

AIX Documentation (PDF)All AIX Commands (fast!)AIX V5.2 Release NotesAIX 5L V5.2 AnnouncementAIX Statement of Direction (PDF)Differences Guide AIX 5.2

Installation Guide AIX 5.2 (PDF)Functional Enh. Summary (PDF)Functional list of AIX commandsProduct Life Cycle Dates AIX 5.2
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2003

POWER4+ Speeds UpIn May 2003 the pSeries 655 and pSeries 670/690 servers are upgraded with faster POWER4+processors. For the first time trial/temporary Capacity Upgrade on Demand (CUoD) is available inthe pSeries (add processors and/or memory on-the-fly).

The original POWER4 chips were made using a 180 nanometer copper/SOI process. The newdual-core POWER4+ chip is made using a 130 nanometer copper/SOI process resulting in ahigher clock speed and a generated heath reduction. The new POWER4+ versions for thepSeries 670/690 machines will run at 1.5GHz and 1.7GHz.The higher performance of the pSeries 670/690 is also due to the introduction of a new optionalRIO-2 (Remote I/O-2) backplane with support for 1GHz I/O busses that support 133MHz PCI-Xperipheral cards. This results in a aggregate I/O bandwidth of 14 GB/sec for the pSeries 670 (was6GB/sec) and 44 GB/sec for the pSeries 690 (was 16GB/sec). The new memory cards of thepSeries 670/690 are twice as dense as prior memory cards. Faster L3-cache runs at 567 MHz.The pSeries 670 now supports up to 256GB of main memory and the pSeries 690 up to 512GB.RIO-2 is also available for the pSeries 650/655.The 4-8 way pSeries 655 supports the 1.5GHz and the 1.7GHz POWER4+ chip and the existing1.1GHz and the 1.3GHz POWER4 chip. The machine starts shipping by the end of May;

upgrades start shipping end of July.The 4-8-16 way pSeries 670 only supports the POWER4+ chip running at 1.5GHz and theexisting 1.1GHz POWER4 chip.The 8-16-32 way pSeries 690 supports the 1.5GHz and the 1.7GHz POWER4+ chip and theexisting 1.1GHz and the 1.3GHz POWER4 chip. The pSeries 670/690 starts shipping by the endof May; upgrades start shipping in August.DLPAR has been improved to support 4 partitions on the pSeries 650/655 (was 2), 16 on thepSeries 670 (was 4) and 32 on the pSeries 690.

Links:pSeries Announcement Brief(PDF)IBM introduces new high-end eServer systems fueled by POWER4+ processorsp690 Descriptionp670 Descriptionp655 Description

IBM pSeries and IBM RS/6000 Performance Report(PDF)pSeries 670/690 with faster POWER4+ and double maximum MemorypSeries 655 with faster POWER4+ and additional Memory OptionspSeries 650 with CUoD and faster Performance using RIO-2 AdaptersCapacity Upgrade on Demand

PowerPC 970The BladeCenter JS20 with PowerPC 970 (PPC 970), 1.6 GHz processors is announcedNovember 11,2003. IBM plans to support AIX in the third quarter of 2004.The 64-bit PowerPC 970, a single-core version of POWER4, can process 200 instructions atonce at speeds of up to 2 GHz and beyond while consuming just tens of watts of power. It is usedin Apple desktops, Apple Xserve servers, imaging applications, and -- increasingly -- innetworking applications.

Links:BladeCenter JS20 Fast 1.6 GHz SMP processor brings POWER technology to the BladeCenter environment

2004 POWER5POWER5-based servers, which will support 64-way SMP and up to 512GB of main memory.POWER5 (code-named Squadron) and POWER6 processors are planned to have an abilitycalled "Fast Path", that takes over tasks that software currently handles more slowly. Theacceleration feature will speed up several communication tasks, including the TCP/IP processingused to read and write data on the Internet, and the Message Passing Interface (MPI), used to
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harness clusters of computers into a collective supercomputer. And the chip will accelerate virtualmemory subsystem, a frequently used operating system feature that manages how higher-speedregular memory can be expanded by using slower but bigger hard drives.POWER5, which will be built initially with 130-nanometer (0.13 micron) features, also will feature"simultaneous multithreading," a feature that allows a single chip to act as two.IBM plans to use POWER5 in "blade" servers as well, super-thin servers stacked densely likebooks in a bookshelf. POWER4 produces 125 watts of power, but a blade processor isconstrained to about 25 to 40 watts."Partitioning," the ability to split a single big server into several smaller ones, will improve.POWER4 permits a partition that's the size of a single processor, but POWER5 will allowhundreds of partitions.Ravi Arimilli (chief technology officer for IBM's Power line) stated in a recent interview that IBM'scoming POWER5 processor was "95 to 97 percent" of the way toward a mainframe processor.Source: eWeek, May 19, 2003Source: CNET, 17/02/03Source: The Register, 17/12/2002Source: ComputerWire, 7/03/2002Source: CNET, 25/04/2002

AIX 5L Version 5.3AIX 5L Version 5.3 is expected somewhere around August 2004.Main features: sub-processor DLPARs (10 LPARs per processor), virtual IO, intra-partition virtualethernet, and shrink filesystem.

2005

2006 POWER6
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Aix History

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