6ELE0068 Lec5 SVHDLolution

8/13/2019 6ELE0068 Lec5 SVHDLolution

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6ELE0068

Microelectronics & VLSI

TEXTIO

Finite State Machines

School of Engineering and

Technology (E&T)


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6ELE0068 This Time

TEXTIO package

o TEXTIO and testbenches

o TEXTIO procedures and functions

o STD_LOGIC_TEXTIO package

Finite State Machine (FSM)

o Moore and Mealy machines

o An implementation example


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6ELE0068 TEXTIO and Testbenches

A VHDL testbench can read test cases from a file andwrite outputs to a file

Files can be opened, closed, appended or read duringsimulation

VHDL supports the reading and writing of text files duringsimulation using a predefined package STD.TEXTIO


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6ELE0068 TEXTIO

Text files are portable

o They can be reused with simulation tools from any vendor

Procedures and functions for reading and writing text filesare included in the package TEXTIO

TEXTIO considers files to be files of lines, where a line istext string terminated by a carriage return

The package defines a number of types that can be usedwith text files

o FILE is defined to hold a text file

o LINE is defined to hold a line of text

To read a set of values from a file, the line is first read,and then the individual elements of the line


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6ELE0068 TEXTIO procedures and functions

Most commonly used procedures and functions


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6ELE0068 File declaration

A file declaration opens a file for input or output,depending on the modeo A file can only be read and written. It cannot be assigned

Input file declaration

Output file declaration

file file_name: text open read_mode is " input_file_name.txt " ;

file file_name: text open write_mode is " output_file_name.txt " ;


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6ELE0068 Use of STD_LOGIC_TEXTIO

Both packages, STD.TEXTIO and IEEE.STD_LOGIC_TEXTIO,

must be used in order to be able to use all the types andfunctions

library ieee;use std.textio.all;use ieee.std_logic_textio.all;----------------------------

Signal A,B: std_logic_vector (2 downto 0);

---------------------------

Stimulus: processfile example: text open read_mode is " input_example.txt " ;

variable L: line ; variable A_var, B_var: std_logic_vector (2 downto 0);

begin

while not endfile (example) loop readline (example, L); read (L, A_var);

read (L, B_var); A


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6ELE0068 Input / Output files example

library ieee ;use ieee .std_logic_1164 .all ;

entity or_gate is port ( A, B : in std_logic ; C : out std_logic );end entity ;

architecture behavior of or_gate is

begin

C


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6ELE0068 Input / Output files example

Library IEEE ;

Use IEEE .std_logic_1164 .all ;Use IEEE .std_logic_textio .all ;Use STD .textio .all ;

entity Testor_gate isend Testor_gate;

architecture stimulus of Testor_gate is

-- UUT component declaration here -- Signals declaration here

begin

-- UUT component instantiation here

STIMULUS0: process file in_file : text open read_mode is "in_values.txt"; file out_file : text open write_mode is "out_values.txt"; variable out_line, in_line : line ;

variable X,Y,Z : std_logic ;

begin while not endfile (in_file) loop --do this till out of data readline (in_file, in_line); --get line from input file read (in_line, X); --get first operand from the line A


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6ELE0068 Finite State Machine (FSM)

A Finite State Machine (FSM) is a model of behaviourcomposed of a finite number of states, transitions betweenthose states, and actions

o Used as a controller in digital circuits

o Consists of a storage element and logic to generate nextstate

Designing of FSMs involves:

o Defining stateso Defining transition between states

State 1

State 2

Transitioncondition 1

Transitioncondition 2

Transition


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6ELE0068 Moore and Mealy Machines

Mealy Machine

o A state machine that determines its outputs from the presentstate and from the inputs

Moore Machine

o A state machine that determines its outputs from thepresent state only

NextStateLogic

StateMemory

OutputLogic

Inputs

clock

Outputs

Current State

(Mealy only)

NextState


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6ELE0068 FSM: An Implementation Example

S_RT=1

S_GT=2

S_YT=3

T=4

S_RY

Reset = 1

Reset = 1

Reset = 1

Reset = 1

T = 1

After 1 min

T = 3

After 1 min

T = 4

After 1 minAfter 1 min

T = 2After initialized


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NextStateLogic

StateMemory

OutputLogic

Reset

clock

LG

Current State

T LY

LR

NextState

entity FSM_for_Traffic_Lights is

port ( Reset, CLK : in std_logic ;T : in integer range 4 downto 0;

LG, LY, LR : out std_logic );end entity FSM_for_Traffic_Lights ;


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NextStateLogic

StateMemory

OutputLogic

Reset

clock

LG

Current State

T LY

LR

NextState

Architecture behaviour of FSM_for_Traffic_Lights is

Type statetype is (s_r, s_ry, s_g, s_y);Signal CurState, NxtState: statetype := s_r;

NSL: process (CurState, T)begin-- Next State Logicend process ;

SM: process (CLK, Reset)begin-- State Memoryend process ; OL: process (CurState)begin-- Output Logicend process ;

end behaviour;


SM: process (CLK, Reset)begin-- State Memoryend process ;

OL: process (CurState)begin-- Output Logicend process ;


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NSL: process (CurState, T) begin

case CurState iswhen s_r => if (T = 1) then NxtState if (T = 2) then

NxtState if (T = 3) then

NxtState if ( T = 4) then NxtState


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SM: process (CLK, Reset) begin

if Reset= 1 then

CurState


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6ELE0068 Solution: FSM for a Washing Machine

entity FSM_for_Washing_Machine isport ( Reset, CLK : in std_logic ;

T : in integer range 5 downto 0; S, W, R, Sp, D : out std_logic );

end FSM_for_Washing_Machine ;

NextStateLogic

StateMemory

OutputLogic

Reset

clock

S

Current State

T W

R

Next

State

Sp

D

T=2

Stop

Wash Rinse

T=4Dry Spin

T=1

T=5

T=2Reset


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6ELE0068

Architecture behaviour of FSM_for_Washing_Machine is

Type statetype is (stop, wash, rinse, spin, dry);Signal CurState, NxtState: statetype := stop;


SM: process (CLK, Reset)begin-- State Memoryend process ; OL: process (CurState)begin-- Output Logicend process ;

end behaviour;


SM: process (CLK, Reset)begin-- State Memoryend process ;

OL: process (CurState)begin-- Output Logicend process ;

NextStateLogic

StateMemory

OutputLogic

Reset

clock

S

Current State

T WR

NextState

Sp

D

Solution: FSM for a Washing Machine


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SM: process (CLK, Reset) begin

if Reset= 1 then CurState


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6ELE0068 Exercise

Different inputs and outputs (Entity declaration)?

VHDL code to implement the circuit modelled using theabove state diagram?


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-- State memory processSM: process (CLK, RESET)

begin

if (RESET='1') then CurState

6ELE0068 Lec5 SVHDLolution

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